MAX9860ETG+ Maxim Integrated Products, MAX9860ETG+ Datasheet - Page 19

IC CODEC MONO AUD 16BIT 24TQFN

MAX9860ETG+

Manufacturer Part Number
MAX9860ETG+
Description
IC CODEC MONO AUD 16BIT 24TQFN
Manufacturer
Maxim Integrated Products
Type
Audio Codecr
Datasheet

Specifications of MAX9860ETG+

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
1 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
81 / 90
Voltage - Supply, Analog
1.7 V ~ 1.9 V
Voltage - Supply, Digital
1.7 V ~ 1.9 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX9860’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1 through 4 for timing diagrams. In
Table 5. Digital Audio Interface Registers
REGISTER ADDRESS
DDLY
DBCI
ABCI
BITS
MAS
TDM
WCI
HIZ
0x06
0x07
______________________________________________________________________________________
Master Mode
0 = The MAX9860 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9860 operates in master mode with LRCLK and BCLK configured as outputs.
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
WCI is ignored when TDM = 1.
DAC BCLK Invert (must be set to ABCI)
In master and slave mode:
0 = SDIN is latched into the part on the rising edge of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK.
In master mode:
0 = LRCLK changes state following the rising edge of BCLK.
1 = LRCLK changes state following the falling edge of BCLK.
DAC Delay Mode
0 = SDIN data is latched on the first BCLK edge following an LRCLK edge.
1 = SDIN data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
DDLY is ignored when TDM = 1.
SDOUT High-Impedance Mode
0 = SDOUT is set either high or low after all data bits have been transferred out of the part.
1 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the part,
Use HIZ only when TDM = 1.
TDM Mode Select
0 = LRCLK signal polarity indicates left and right audio.
1 = LRCLK is a framing pulse which transitions polarity to indicate the start of a frame of audio data
W hen op er ati ng i n TD M m od e the l eft channel i s outp ut i m m ed i atel y fol l ow i ng the fr am e sync p ul se. If r i g ht-
channel d ata i s b ei ng tr ansm i tted , the 2nd channel of d ata i m m ed i atel y fol l ow s the 1st channel d ata.
ADC BCLK Invert (must be set to DBCI)
0 = SDOUT is valid on the rising edge of BCLK and transitions immediately after the rising edge.
1 = SDOUT is valid on the falling edge of BCLK and transitions immediately after the falling edge.
Digital Audio Interface
following an LRCLK edge (I
allowing SDOUT to be shared by other devices.
consisting of multiple channels.
MAS
B7
0
16-Bit Mono Audio Voice Codec
WCI
B6
0
DBCI
ABCI
2
B5
S-compatible mode).
master mode, the MAX9860 outputs LRCLK and BCLK,
while in slave mode, they are inputs. When operating in
master mode, BCLK can be configured in a number of
ways to ensure compatiblity with other audio devices.
DDLY
ADLY
B4
FUNCTION
HIZ
B3
ST
TDM
B2
BSEL
B1
0
B0
0
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