MAX9860ETG+ Maxim Integrated Products, MAX9860ETG+ Datasheet - Page 35

• Manufacturer Part Number: MAX9860ETG+
• Description: IC CODEC MONO AUD 16BIT 24TQFN
• Manufacturer: Maxim Integrated Products
• Type: Audio Codecr

Specifications of MAX9860ETG+

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 81 / 90
• Voltage - Supply, Analog: 1.7 V ~ 1.9 V
• Voltage - Supply, Digital: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

feature allows all registers to be read sequentially within
one continuous frame. A STOP (P) condition can be
issued after any number of read data bytes. If a STOP
condition is issued followed by another read operation,
the first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9860’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START (Sr) condition is
then sent followed by the slave address with the R/W bit
set to 1. The MAX9860 then transmits the contents of
the specified register. The address pointer autoincre-
ments after transmitting the first byte.
Figure 10. Writing N Bytes of Data to the MAX9860
Figure 11. Reading One Byte of Data from the MAX9860
Figure 12. Reading N Bytes of Data from the MAX9860
S
ACKNOWLEDGE FROM MAX9860
S
S
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
SLAVE ADDRESS
SLAVE ADDRESS
SLAVE ADDRESS
______________________________________________________________________________________
R/W
R/W
R/W
0
0
0
A
A
A
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
REGISTER ADDRESS
REGISTER ADDRESS
REGISTER ADDRESS
16-Bit Mono Audio Voice Codec
REPEATED START
REPEATED START
A
Sr
A
ACKNOWLEDGE FROM MAX9860
A
ACKNOWLEDGE FROM MAX9860
B7 B6
Sr
ACKNOWLEDGE FROM MAX9860
SLAVE ADDRESS
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 11 illustrates the frame format for reading
one byte from the MAX9860. Figure 12 illustrates the
frame format for reading multiple bytes from the
MAX9860.
B5 B4
SLAVE ADDRESS
DATA BYTE 1
1 BYTE
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
B3 B2
R/W
B1 B0
1
R/W
A
A
1
NOT ACKNOWLEDGE FROM MASTER
A
ACKNOWLEDGE FROM MAX9860
B7 B6
DATA BYTE
DATA BYTE
B5 B4
1 BYTE
1 BYTE
DATA BYTE n
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
1 BYTE
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
B3 B2
B1 B0
A
A
P
A
P
P
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