AD1938YSTZ Analog Devices Inc, AD1938YSTZ Datasheet
AD1938YSTZ
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AD1938YSTZ Summary of contents
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FEATURES PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N 3.3 V single supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz ...
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AD1938 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Test Conditions ............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 4 Digital ...
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SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages (AVDD, DVDD) 3.3 V Temperature range 1 as specified in Table 1 and Table 2 Master clock 12.288 ...
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AD1938 Parameter Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Specifications measured at a case temperature of 125°C. Table ...
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DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < +125°C, DVDD = 3.3 V ± 10%. C Table 4. Parameter High Level Input Voltage ( High Level Input Voltage ( Low Level Input Voltage ( Input ...
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AD1938 DIGITAL FILTERS Table 6. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode All modes, typical ...
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TIMING SPECIFICATIONS −40°C < T < +125°C, DVDD = 3.3 V ± 10%. C Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET MCLK f MCLK t PDR t PDRR PLL Lock time 256 f ...
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AD1938 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND MCLKI/XI MCLKO/XO AGND AVDD OR3 OR4 PD/RST DSDATA4 DGND Table 10. Pin Function Descriptions Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground MCLKI/XI Master Clock Input/Crystal Oscillator Input ...
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AD1938 Pin No. In/Out Mnemonic Description 29 O OR1 DAC 1 Right Output OL2 DAC 2 Left Output OR2 DAC 2 Right Output AGND Analog Ground AVDD Analog Power Supply. Connect to ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 2000 4000 6000 8000 10000 12000 FREQUENCY (Hz) Figure 3. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD1938 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 192 kHz 32 64 Rev Page –2 –4 –6 –8 –10 ...
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THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCS) There are four ADC channels in the AD1938 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ...
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AD1938 the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN The function of the RST pin sets all the control registers to their default settings. To avoid pops, reset does not power ...
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POWER SUPPLY AND VOLTAGE REFERENCE The AD1938 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the ...
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AD1938 Table 12. Pin Function Changes in TDM-AUX Modes Mnemonic Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data In ALRCLK ADC LRCLK In/ADC ...
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ALRCLK ABCLK DSDATA1 DAC L1 DAC R1 (TDM_IN) 4 ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 (TDM_OUT) 32 BITS MSB DLRCLK LEFT (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ALRCLK ABCLK 4 ON-CHIP ADC CHANNELS ...
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AD1938 ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM_IN) 4 ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 ADC L2 ADC R2 (TDM_OUT) DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ASDATA2 MSB (AUX1_OUT) DSDATA4 ...
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DAISY-CHAIN MODE The AD1938 allows a daisy-chain configuration to expand the system to 8 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512 f . The first eight slots of the DAC S TDM ...
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AD1938 DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 DAC L1 DAC R1 (IN) DSDATA2 (OUT) DSDATA3 DAC L3 DAC R3 (IN) DSDATA4 (OUT) 32 BITS MSB FIRST SECOND AD193x AD193x Figure 19. Dual-Line DAC ...
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ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN ASDATA1 (TDM_OUT OF THE SECOND AD193x ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2 IN THE CHAIN) ASDATA2 (TDM_IN OF THE ...
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AD1938 t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATAx LEFT-JUSTIFIED MSB MODE t DDH DSDATAx 2 I S-JUSTIFIED MODE DSDATAx RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATAx LEFT-JUSTIFIED MSB MODE ASDATAx ...
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Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Mnemonic Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data ...
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AD1938 CONTROL REGISTERS DEFINITIONS The global address for the AD1938 is 0x04, shifted left one bit due to the R/ W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. ...
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Table 17. PLL and Clock Control Register 1 Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS ...
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AD1938 Table 20. DAC Control Register 2 Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4 Reserved ...
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ADC CONTROL REGISTERS Table 23. ADC Control Register 0 Bit Value Function 0 0 Normal 1 Power down 1 0 Off Unmute 1 Mute 3 0 Unmute 1 Mute 4 0 Unmute 1 Mute 5 0 ...
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AD1938 Table 25. ADC Control Register 2 Bit Value Function 0 0 50/50 (allows 32, 24, 20 bit clocks (BCLKs) per channel) 1 Pulse (32 BCLKs per channel Drive out on falling edge (DEF) 1 Drive ...
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ADDITIONAL MODES The AD1938 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM ...
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AD1938 APPLICATIONS CIRCUITS Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure ...
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... EVAL-AD1938AZ RoHS Compliant Part. 2 For the AD1938YSTZ, AD1938YSTZRL, AD1938WBSTZ, and AD1938WBSTZRL: single-ended output; SPI control port Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD1938WBSTZ and AD1938WBSTZRL models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models ...
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AD1938 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05582-0-1/11(C) Rev Page ...