AD1938YSTZ Analog Devices Inc, AD1938YSTZ Datasheet - Page 13

• Manufacturer Part Number: AD1938YSTZ
• Description: IC CODEC 24BIT 4ADC/8DAC 48LQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of AD1938YSTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 4 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 94 / 94
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 106
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Audio
• No. Of Adcs: 4
• No. Of Dacs: 8
• No. Of Input Channels: 4
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four ADC channels in the AD1938 configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs
include on-board digital antialiasing filters with 79 dB stop-
band attenuation and linear phase response, operating at an
oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz
modes). Digital outputs are supplied through two serial data
output pins (one for each stereo pair) and a common frame
clock (ALRCLK) and bit clock (ABCLK). Alternatively, one of
the TDM modes can be used to access up to 16 channels on a
single TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to inter-
nal switched capacitors. To isolate the external driving op amp
from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for example, ceramic NPO or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a
1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The
cutoff frequency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The AD1938 DAC channels are arranged as single-ended, four
stereo pairs giving eight analog outputs for minimum external
components. The DACs include on-board digital reconstruction
filters with 70 dB stop-band attenuation and linear phase response,
operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes)
or 2 (192 kHz mode). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through four serial data
input pins (one for each stereo pair), a common frame clock
(DLRCLK), and a bit clock (DBCLK). Alternatively, one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins. The
use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band; therefore, exercise care in selecting these components.
Rev. C | Page 13 of 32
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI/XI pin. The default at power-up
is 256 × f
clock frequency stays at the same absolute frequency; therefore,
the actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD193x family is programmed in 256 × f
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD193x is then switched to 96 kHz operation (by writing
to the SPI port), the frequency of the master clock should
remain at 12.288 MHz, which becomes 128 × f
mode, this becomes 64 × f
The internal clock for the ADCs is 256 × f
The internal clock for the DACs varies by mode: 512 × f
mode), 256 × f
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × f
mode) master clock can be used for either the ADCs or DACs if
selected in the PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock
stabilizes.
The internal master clock can be disabled in the PLL and Clock
Control 0 register to reduce power dissipation when the
AD1938 is idle. The clock should be stable before it is enabled.
Unless a standalone mode is selected (see the Serial Control
Port section), the clock is disabled by reset and must be enabled
by writing to the SPI port for normal operation.
To maintain the highest performance possible, limit the clock
jitter of the internal master clock signal to less than a 300 ps rms
time interval error (TIE). Even at these levels, extra noise or
tones can appear in the DAC outputs if the jitter spectrum
contains large spectral peaks. If the internal PLL is not used, it
is best to use an independent crystal oscillator to generate the
master clock. In addition, it is especially important that the
clock signal not pass through an FPGA, CPLD, or other large
digital chip (such as a DSP) before being applied to the
AD1938. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals. When the PLL is used, jitter in
S
from the MCLKI/XI pin. In 96 kHz mode, the master
S
(96 kHz mode), or 128 × f
S
.
S
(referenced to 48 kHz
S
S
for all clock modes.
(192 kHz mode). By
S
. In 192 kHz
S
AD1938
mode, the
S
(48 kHz