TLV32014KIDBTRG4

Manufacturer Part NumberTLV32014KIDBTRG4
DescriptionIC CODEC AUDIO MONO LP 30-TSSOP
ManufacturerTexas Instruments
TypeVoice-Band Codec
TLV32014KIDBTRG4 datasheet
 


Specifications of TLV32014KIDBTRG4

Data InterfaceSerialResolution (bits)16 b
Number Of Adcs / Dacs1 / 1Sigma DeltaYes
S/n Ratio, Adcs / Dacs (db) Typ84 / 92Voltage - Supply, Analog2.7 V ~ 3.6 V
Voltage - Supply, Digital1.65 V ~ 1.95 VOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case30-TFSOP (0.173", 4.40mm Width)
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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LOW-POWER, HIGHLY-INTEGRATED, PROGRAMMABLE
FEATURES
Mono 16-Bit Oversampling Sigma-Delta A/D
Converter
Mono 16-Bit Oversampling Sigma-Delta D/A
Converter
Support Maximum Master Clock of 100 MHz to
Allow the DSP Output Clock to be Used as a
Master Clock
Selectable FIR/IIR Filter With Bypassing
Option
Programmable Sampling Rate up to:
– Max 26 Ksps With On-Chip IIR/FIR Filter
– Max 104 Ksps With IIR/FIR Bypassed
On-Chip FIR Produced 84-dB SNR for ADC
and 92-dB SNR for DAC
Smart Time Division Multiplexed
(SMARTDM™) Serial Port
– Glueless 4-Wire Interface to DSP
– Automatic Cascade Detection (ACD)
Self-Generates Master/Slave Device
Addresses
– Programming Mode to Allow On-the-Fly
Reconfiguration
– Continuous Data Transfer Mode to
Minimize Bit Clock Speed
– Support Different Sampling Rate for Each
Device
– Turbo Mode to Maximize Bit Clock for
Faster Data Transfer and Allow Multiple
Serial Devices to Share the Same Bus
– Allows up to 16 Devices to be Connected
to a Single Serial Port
Host Port
– 2-Wire Interface
2
2
– Selectable I
C or S
C
Differential and Single-Ended Analog
Input/Output
Built-In Analog Functions:
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SMARTDM, TMS320C5000, TMS320C6000 are trademarks of Texas Instruments.
TMS320 is a trademark of Texas Instrument.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
16-Bit, 26-KSPS MONO CODEC
– Analog and Digital Sidetone
– Antialiasing Filter (AAF)
– Programmable Input and Output Gain
Control (PGA)
– Microphone/Handset/Headset Amplifiers
– AIC12K has an 8-
– Power Management With
Hardware/Software Power-Down Modes
30 µW
Separate Software Control for ADC and DAC
Power Down
Fully Compatible With Common TMS320™
DSP Family and Microcontroller Power
Supplies
– 1.65 V - 1.95 V Digital Core Power
– 1.1 V - 3.6 V Digital I/O
– 2.7 V - 3.6 V Analog
Power Dissipation (P
– 11.2 mW at 3.3 V in Standard Operation
– 17.8 mW at 3.3 V With Headphone Drivers
Internal Reference Voltage (V
2s Complement Data Format
Test Modes Which Include Digital Loopback
and Analog Loopback
APPLICATIONS
Digital Still Cameras
Wireless Accessories
Hands-Free Car Kits
VOIP
Cable Modem
TLV320AIC12, TLV320AIC13
TLV320AIC14, TLV320AIC15
TLV320AIC12K, TLV320AIC14K
SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007
Speaker Driver
)
D
)
ref
Copyright © 2001–2007, Texas Instruments Incorporated

TLV32014KIDBTRG4 Summary of contents

  • Page 1

    ... Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SMARTDM, TMS320C5000, TMS320C6000 are trademarks of Texas Instruments. TMS320 is a trademark of Texas Instrument. PRODUCTION DATA information is current as of publication date. ...

  • Page 2

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent ...

  • Page 3

    AIC12/13/12K DBT PACKAGE (TOP VIEW) IOVSS 1 30 IOVDD 2 29 FSD DOUT 5 26 DIN PWRDN 9 22 OUTM1 OUTP1 DRVDD 12 ...

  • Page 4

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 TERMINAL NAME AIC12/13/12K AIC14/15/14K DBT DBT NO. NO. IOVSS 1 1 IOVDD 2 2 FSD DOUT 5 5 DIN 6 6 ...

  • Page 5

    TERMINAL NAME AIC12/13/12K AIC14/15/14K DBT DBT NO. NO. SCLK 28 28 DVDD 29 29 DVSS – 13, 14, 15 Electrical Characteristics AIC12, AIC13, AIC14, AIC15, AIC12K, AIC14K: Over Recommended Operating Free-Air Temperature Range AVDD = 3.3 ...

  • Page 6

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Recommended Operating Conditions Supply voltage for analog, AVDD Supply voltage for analog output driver, DRVDD V SS Supply voltage for digital core, DVDD Supply voltage for ...

  • Page 7

    Digital Inputs and Outputs kHz, Outputs Not Loaded s PARAMETER V High-level output voltage, DOUT OH V Low-level output voltage, DOUT OL I High-level input current, any digital input IH I Low-level input current, any digital ...

  • Page 8

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 ADC DYNAMIC PERFORMANCE ( KHz PARAMETER SNR Signal-to-noise ratio THD Total harmonic distortion Signal-to-harmonic THD+N distortion + noise (1) The test condition is ...

  • Page 9

    DAC Path Filter (1) ( KHz PARAMETER CONDITIONS 300 Filter gain relative to gain at 1020 Hz (1) The filter gain outside of the passband is measured ...

  • Page 10

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 DAC Channel Characteristics PARAMETER Dynamic range Interchannel isolation E Gain error Common mode voltage Idle channel narrow band noise V Output offset voltage ...

  • Page 11

    Power-Supply Rejection PARAMETER AV Supply-voltage rejection ratio, analog supply ( Supply-voltage rejection ratio, DAC channel DD (1) Power supply rejection measurements are made with both the ADC and DAC channels idle and a 200 mV peak-to-peak ...

  • Page 12

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 s2d MICIN Preamplifier INP2 24, 12 INM2 MUX INP1 INM1 Analog Loopback OUTP1 PGA (600 Driver) OUTM1 - ...

  • Page 13

    Functional Block Diagram AIC14/15/14k 2 MICIN s d Preamplifier INP2 24, 12 INM2 MUX INP1 INM1 Analog Loopback OUTP1 PGA (600 Driver) OUTM1 − Step Size = 1 dB BIAS 1.35 ...

  • Page 14

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Definitions and Terminology Term Definition Data Transfer The time during which data is transferred from DOUT and to DIN. The interval Interval is 16 shift clocks ...

  • Page 15

    MCLK RESET SCLK FSD t en DOUT t h2 DIN Figure 2. Serial Communication Timing t Pulse duration, MCLK high wH t Pulse duration, MCLK low wL Setup time, RESET, before MCLK high t ...

  • Page 16

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 SDA LOW SCL t HD;STA t HD;DAT t SCL clock frequency SCL t Hold time (repeated START condition. After this HD;STA ...

  • Page 17

    Parameter Measurement Information (continued) 0 -20 -40 -60 -80 -100 -120 -140 -160 0 500 1000 Figure 5. FFT—ADC Channel (-9 dB Input) 0 -20 -40 -60 -80 -100 -120 -140 -160 0 500 1000 Figure 6. FFT—DAC Channel ...

  • Page 18

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Parameter Measurement Information (continued) 0 -20 -40 -60 -80 -100 -120 -140 0 2000 Figure 8. FFT—ADC Channel in FIR/IIR Bypass Mode (-1 dB Input) 0 ...

  • Page 19

    ADC FILTER GAIN vs FREQUENCY RESPONSE (FIR −5 −10 −15 −20 −25 −30 0 500 1000 1500 2000 2500 3000 3500 4000 f − Frequency − Hz Figure 10. ADC IIR FILTER GROUP DELAY vs FREQUENCY 9 ...

  • Page 20

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 TYPICAL CHARACTERISTICS (continued) ADC FILTER GAIN vs FREQUENCY (FIR/IIR BYPASS -10 -12 -14 0 2000 4000 6000 8000 10 ...

  • Page 21

    TYPICAL CHARACTERISTICS (continued) DAC FIR vs FREQUENCY RESPONSE 20 0 −20 −40 −60 −80 −100 −120 −140 0 1000 2000 3000 4000 5000 6000 7000 8000 f − Frequency − Hz Figure 18. Operating Frequencies (see Notes) The sampling ...

  • Page 22

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 MCLK 1/P (no_dev x mode) / (MNP) * SCLK may not be an uniform clock depending upon values of devnum, mode, and MNP ...

  • Page 23

    Decimation Filter The decimation filters are either FIR filters or IIR filters selected by bit D5 of the control register 1. The FIR filter provides linear-phase output with 17/f negligible group delay. The decimation filters reduce the digital data ...

  • Page 24

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 MIC Input TLV320AIC1x supports single ended microphone input. This can be used by connecting the external single ended source through ac coupling to the MICIN pin. ...

  • Page 25

    Analog Output The OUTP and OUTM are differential output from the DAC channel. The OUTP1 and OUTM1 can drive a load of 600- directly and be either differential or single-ended (see from two audio amplifiers to drive low-voltage speakers ...

  • Page 26

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 SPEAKER DRIVER CONFIGURATION Differential IIR/FIR Control Overflow Flags The decimation IIR/FIR filter sets an overflow flag (bit D7) of control register 1 indicating that the input ...

  • Page 27

    To calculate the channel address, during the first 64 MCLKs, the device counts the number of clocks between ACD starting (reset) and the FSD going high. During the next 64 MCLKs, the device counts the number of clocks till ...

  • Page 28

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Table 1. SMARTDM Device Addresses (continued) TOTAL CODECS 1100 14 ...

  • Page 29

    I C Write Sequence SCL SDA ACK I2C I2C I2C Start Bit = 0 SMARTDM Device Address 11111 = Broadcast Mode (see Table 1) Programmable I C ...

  • Page 30

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Write Mode 7 Bit 1 Bit 2 S/ Device Address (3 Bit)+ R/W Dtdmsp Device Address (+) = 0 Read Mode 7 Bit 1 ...

  • Page 31

    Digital Interface Clock Source (MCLK, SCLK) MCLK is the external master clock input. The clock circuit generates and distributes necessary clocks throughout the device. SCLK is the bit clock used to receive and transmit data synchronously. When the device ...

  • Page 32

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 the master's FS. The master FSD is output to the first slave and the first slave's FSD is output to the second slave device and so ...

  • Page 33

    Asynchronous Sampling (Codecs in cascade are sampled at different sampling frequency) The 'AIC1x SMARTDM supports a different sampling frequency between the codecs in cascade connecting to a single serial port. All codecs are required to have a common frame ...

  • Page 34

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Master FS Master DIN/DOUT Master FSD, Slave 2 FS Slave 2 FSD, Slave 1 FS Slave 1 FSD, Slave 0 FS Slave 0 FSD, (see Note) ...

  • Page 35

    Slot 0 1 Number SCLK FS DIN/ DOUT Master Slave Slave n-2 n-3 NOTE the total number of AIC12s in the cascade Figure 35. Standard Operation/Programming Mode: Master-Slave Cascade Timing Continuous Data Transfer Mode The continuous data ...

  • Page 36

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Slot Number SCLK FS DIN/ DOUT Master Slave Slave n-2 n-3 Data Frame / Sample 1 NOTE the total number of ...

  • Page 37

    TURBO PROGRAMMING MODE Stand-Alone Case: Turbo SCLK One SCLK FS Data Frame Control Frame ... ... DIN / DOUT Cascade Case (Master + 4 Slaves): Turbo SCLK FS Data Frame DIN / DOUT ...

  • Page 38

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Data Frame Format (15+1) Bit Mode (Continuous Data Transfer Mode Only) (16 Bit A/D Data) 16 Bit Mode 16 Bit Mode Control Frame Format (Programming Mode) ...

  • Page 39

    Master FS Data Frame DIN Slave0 Master Slave2 Time Slot Write Command A. NOTE: In this example, the broadcast operation (D11 = 1) is used to program the four control registers of Reg.1, Reg.2, Reg.4, and Reg.6 in all ...

  • Page 40

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 (1) Control Register ADOVF CX IIR R R/W R/W (1) NOTE Read Write RESET BIT NAME FUNCTION VALUE ...

  • Page 41

    Control Register 2 Bit Summary (continued) RESET BIT NAME FUNCTION VALUE D2 GPO 0 General-purpose output D1-D0 HPC 00 Host port control bits. Write the following values into D1-D0 to select the appropriate configuration for two pins SDA and ...

  • Page 42

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Control Register 4 Bit Summary (continued) RESET BIT NAME VALUE (1) (2) D6-D0 MNP — Divider values and used in ...

  • Page 43

    Table 5. A/D PGA Gain (continued ...

  • Page 44

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 (1) Control Register ...

  • Page 45

    Table 6. D/A PGA Gain (continued ...

  • Page 46

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 (1) Control Register R/W R/W R/W (1) NOTE Read Write ...

  • Page 47

    Control Register PSDO MUTE2 MUTE3 R/W R/W R/W RESET BIT NAME FUNCTION VALUE D7 PSDO 0 Programmable single-ended/differential output. This bit configures the two pins of OUTP2 and OUTP3 as single-ended or differential output. If ...

  • Page 48

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Microphone 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 600 3.3 V Analog Supply 0.1 F Analog GND 3.3 V Analog Supply 0.1 F ...

  • Page 49

    Microphone 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 600 600 3.3 V Analog Supply 0.1 F Analog GND 3.3 V Analog Supply 0.1 F Analog GND Figure 43. Pseudo-Differential Microphone Input (External ...

  • Page 50

    TLV320AIC12, TLV320AIC13 TLV320AIC14, TLV320AIC15 TLV320AIC12K, TLV320AIC14K SLWS115E – OCTOBER 2001 – REVISED JANUARY 2007 Layout and Grounding Guidelines for TLV320AIC1x TLV320AIC1x has an in-built analog antialias filter, which provides rejection to external noise at high frequencies that may couple into ...

  • Page 51

    ... PACKAGING INFORMATION (1) Orderable Device Status TLV32012KIDBTRG4 ACTIVE TLV32014KIDBTRG4 ACTIVE TLV320AIC12CDBT NRND TLV320AIC12CDBTG4 NRND TLV320AIC12CDBTR NRND TLV320AIC12CDBTRG4 NRND TLV320AIC12IDBT NRND TLV320AIC12IDBTG4 NRND TLV320AIC12IDBTR NRND TLV320AIC12IDBTRG4 NRND TLV320AIC12KIDBT ACTIVE TLV320AIC12KIDBTG4 ACTIVE TLV320AIC12KIDBTR ACTIVE TLV320AIC12KIRHBR ACTIVE TLV320AIC12KIRHBT ACTIVE TLV320AIC13CDBT NRND TLV320AIC13CDBTG4 NRND TLV320AIC13CDBTR ...

  • Page 52

    Orderable Device Status TLV320AIC14IDBT NRND TLV320AIC14IDBTG4 NRND TLV320AIC14IDBTR NRND TLV320AIC14IDBTRG4 NRND TLV320AIC14KIDBT ACTIVE TLV320AIC14KIDBTG4 ACTIVE TLV320AIC14KIDBTR ACTIVE TLV320AIC15IDBT NRND TLV320AIC15IDBTG4 NRND TLV320AIC20CPFB NRND TLV320AIC20CPFBG4 NRND TLV320AIC20CPFBR NRND TLV320AIC20CPFBRG4 NRND TLV320AIC20IPFB NRND TLV320AIC20IPFBG4 NRND TLV320AIC20IPFBR NRND TLV320AIC20IPFBRG4 NRND TLV320AIC21CPFB ...

  • Page 53

    Orderable Device Status TLV320AIC24CPFBG4 NRND TLV320AIC24CPFBR NRND TLV320AIC24CPFBRG4 NRND TLV320AIC24IPFB NRND TLV320AIC24IPFBG4 NRND TLV320AIC24IPFBR NRND TLV320AIC24IPFBRG4 NRND TLV320AIC25CPFB NRND TLV320AIC25CPFBG4 NRND TLV320AIC25CPFBR NRND TLV320AIC25CPFBRG4 NRND TLV320AIC25IPFB NRND TLV320AIC25IPFBG4 NRND TLVAIC12KIRHBRG4 ACTIVE TLVAIC12KIRHBTG4 ACTIVE (1) The marketing status values ...

  • Page 54

    TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken ...

  • Page 55

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TLV320AIC12CDBTR TSSOP DBT TLV320AIC12IDBTR TSSOP DBT TLV320AIC12KIDBTR TSSOP DBT TLV320AIC12KIRHBR QFN RHB TLV320AIC12KIRHBT QFN RHB TLV320AIC13CDBTR TSSOP DBT TLV320AIC14CDBTR TSSOP DBT TLV320AIC14IDBTR TSSOP DBT TLV320AIC14KIDBTR TSSOP ...

  • Page 56

    Device Package Type TLV320AIC12CDBTR TSSOP TLV320AIC12IDBTR TSSOP TLV320AIC12KIDBTR TSSOP TLV320AIC12KIRHBR QFN TLV320AIC12KIRHBT QFN TLV320AIC13CDBTR TSSOP TLV320AIC14CDBTR TSSOP TLV320AIC14IDBTR TSSOP TLV320AIC14KIDBTR TSSOP TLV320AIC20CPFBR TQFP TLV320AIC20IPFBR TQFP TLV320AIC21CPFBR TQFP TLV320AIC21IPFBR TQFP TLV320AIC24CPFBR TQFP TLV320AIC24IPFBR TQFP TLV320AIC25CPFBR TQFP ...

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    PFB (S-PQFP-G48) 0, 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 62

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  • Page 63

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...