IC STEREO AUDIO CODEC LP 80-BGA

TLV320AIC10CGQER

Manufacturer Part NumberTLV320AIC10CGQER
DescriptionIC STEREO AUDIO CODEC LP 80-BGA
ManufacturerTexas Instruments
TypeGeneral Purpose
TLV320AIC10CGQER datasheet
 


Specifications of TLV320AIC10CGQER

Data InterfaceSerialResolution (bits)16 b
Number Of Adcs / Dacs1 / 1Sigma DeltaYes
S/n Ratio, Adcs / Dacs (db) Typ90 / 87Dynamic Range, Adcs / Dacs (db) Typ82 / 82
Voltage - Supply, Analog3 V ~ 5.5VVoltage - Supply, Digital3 V ~ 5.5 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case80-BGA MICROSTAR JUNIORAudio Codec TypeMono
No. Of Adcs1No. Of Dacs1
No. Of Input Channels2No. Of Output Channels1
Adc / Dac Resolution16bitAdcs / Dacs Signal To Noise Ratio90dB
Sampling Rate22kSPSFor Use With296-10701 - EVAL MOD FOR TLV320AIC10
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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General Purpose 3 V to 5.5 V
16 Bit 22 KSPS DSP CODEC
TLV320AIC10
Data Manual
December 2001
HPA Data Acquisition
SLWS093F

TLV320AIC10CGQER Summary of contents

  • Page 1

    General Purpose 5 Bit 22 KSPS DSP CODEC TLV320AIC10 December 2001 Data Manual HPA Data Acquisition SLWS093F ...

  • Page 2

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment ...

  • Page 3

    Section 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 4

    Multiplexed Analog Input and Output 2.8.1 2.8.2 2.8.3 2.8.4 3 Serial Communications 3.1 Primary Serial Communication 3.2 Secondary Serial Communication 3.2.1 3.2.2 3.2.3 3.3 Direct Configuration Mode 3.4 Continuous Data Transfer Mode 3.5 DIN and DOUT ...

  • Page 5

    Parameter Measurement Information 6 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

  • Page 6

    Direct Configuration Mode Timing 3–10 Continuous Data Transfer Mode Timing 3–11 Primary Communication DIN and DOUT Data Format 3–12 Secondary Communication DIN and DOUT Data Format 3–13 Direct Communication DCSI Data Format 5–1 FC, FS and FSD Timing 5–2 ...

  • Page 7

    Introduction The TLV320AIC10 provides high resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. It allows 2-to-1 MUX inputs with built-in antialiasing filter and amplification for general-purpose applications such as telephone hybrid interface, electret ...

  • Page 8

    Glueless serial port interface to DSPs (TI TMS320Cxx, SPI, or standard DSPs) Automatic cascading detection (ACD) makes cascade programming simple and allows devices to be connected in cascade. On-fly reconfiguration modes include secondary-communication mode and direct-configuration mode ...

  • Page 9

    Functional Block Diagram Receiver or MIC Amp AURXFP SW5 SW6 SW4 + AURXCP A1 – Note: Switches SWx are Controlled by Bit D6 of Control Register 1. SW2 SW3 AURXM SW1 INP Anti– MUX Aliasing Filter INM VMID @ ...

  • Page 10

    Terminal Assignments AURXFP AURXM AURXCP DTXOP DTXOM DTXIP DTXIM OUTP OUTM M0 M1 PWRDWN NOTE: All NC pins should be left unconnected. 1–4 PFB PACKAGE (TOP VIEW ...

  • Page 11

    Terminal Assignments (Continued AURXFP AVDD1 C AURXCP AURXM D DTXOM DTXOP E DTXIM DTXIP F OUTP OUTM PWRDWN NC J NOTE: All NC pins should be left unconnected. 1.4 Ordering Information ...

  • Page 12

    Terminal Functions TERMINALS I/O I/O NO. NAME NAME PFB GQE I/O ALTIN Serial input in the event monitor mode. Tie this pin to low if not used. AURXCP Receiver-path/GP amplifier noninverting input. It ...

  • Page 13

    Terminal Functions (Continued) TERMINALS I/O I/O NO. NAME NAME PFB GQE I/O MCLK Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit. M Master/slave select input. When M/S is ...

  • Page 14

    DAC channel DAC channel refers to all signal-processing circuits between the digital data word applied to DIN and the differential output analog signal available at OUTP and OUTM. Host A host is any processing system that interfaces to DIN, DOUT, ...

  • Page 15

    Functional Description 2.1 Device Functions 2.1.1 Operating Frequencies The sampling frequency represented by the frequency of the primary communication is derived from the master clock (MCLK) input with the following equation Sampling (conversion) frequency = MCLK/(256 The ...

  • Page 16

    Primary 16 SCLKs FS DOUT 16–bit ADC Data (16-bit) DOUT 15–bit ADC Data + M/S (15+1-bit) # SCLKs (See Note B) NOTES: A. M/S bit (D15) in the secondary communication is used to indicate whether the register data (address and ...

  • Page 17

    SCLK FS DIN (16-bit) DIN (15+1-bit) NOTE means no secondary-communication request (software secondary-request control, see Section 3.2). Figure 2–3. Timing Sequence of DAC Channel (Primary Communication Only) Primary 16 SCLKs FS DIN (16-bit) 16–bit DAC Data ...

  • Page 18

    MIC Input The auxiliary inputs (AURXFP, AURXCP, and AURXM) can be programmed to interface with a microphone such as an electret microphone, as illustrated in Figure 2.5, by writing bit D6 and D4 of control register ...

  • Page 19

    Analog and Digital Loopback The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used for in-circuit system level tests. The analog loopback routes the DAC low-pass filter output into the ...

  • Page 20

    Reset and Power-Down Functions 2.2.1 Software and Hardware Reset The TLV320AIC10 resets the internal counters and registers in response to either of two events: A low-going reset pulse is applied to terminal RESET written to the ...

  • Page 21

    Clock Source MCLK is the external master-clock input. The clock circuit generates and distributes the necessary clocks throughout the device. When the device is in the master mode, SCLK and FS are output and derived from MCLK in order ...

  • Page 22

    The TLV320AIC10 has four serial-interface modes that support most modern DSP engines. This modes can be selected by M0 and M1. In mode 0 (Figure 2–8 one-bit wide and it is active high one SCLK period before the ...

  • Page 23

    SCLK FS DIN/DOUT (16-bit) MSB Figure 2–11. Timing Diagram for the FS Frame Mode (M1M0 = 11) NOTE: In frame mode, if AIC10 is in slave mode, DIN/DOUT should be delayed by one SCLK from the falling edge of ...

  • Page 24

    Frame-Sync (FS) Function—Slave Mode The slave mode is selected by connecting pin M/S to LO. The frame-sync timing is generated externally by the master, as shown in Figure 2–13 (that is, FSD) and is applied the ...

  • Page 25

    P Master FS M Master FSD, Slave 2 FS Slave 2 FSD, Slave 1 FS Slave 1 FSD, Slave 0 FS Slave 0 FSD (See Note) Figure 2–15. Master-Slave Frame-Sync Timing 2.8 Multiplexed Analog Input and Output The two differential ...

  • Page 26

    Analog Output OUTP and OUTM are differential outputs and can typically drive a 600- load directly. Figure 2–17 shows the circuit when the load is ground-referenced. OUTM OUTP Figure 2–17. Differential Output Drive (Ground-Referenced 2.8.3 Single-Ended Analog Input The ...

  • Page 27

    Serial Communications DOUT, DIN, SCLK, SXCLK, FS, and Fc are the serial communication signals. SCLK is used to perform internal processing and data transfer for serial interface between AIC10 and DSP. In the pulse/frame FS mode, there are 256 ...

  • Page 28

    Secondary Serial Communication Secondary serial communication is used to read or write 16-bit words that program both the options and the circuit configurations of the device. Register programming always occurs during secondary communication. Four primary and secondary communication cycles ...

  • Page 29

    Register Programming All register programming occurs during secondary communication through DIN or ALTI, and data are latched and valid on the falling edge of the SCLK during the frame-sync signal. If the default value of a particular register is ...

  • Page 30

    To program control register 1, the following procedure must be performed through DIN: Request secondary communication by setting either D0=1(software request high (hardware request) during the primary communication interval. At the secondary communication interval (FS), send data ...

  • Page 31

    P P Master (FC pulse needs to be inserted any time within the primary communication) FC (See Note) NOTES master device and slave devices should be connected together B. Primary communication interval = 256 ...

  • Page 32

    CLKX0 DX0 FSX1 FSR1 DX1 DR1 CLKX1 CLKR1 TMS320C54XX MCLK BFSX0 BFSR0 BDX0 BDR0 BCLKX0 BCLKR0 TMS320C5402 3–6 DVDD 1 k DCSI M/S DVDD FS FSD DIN DOUT SCLK TLV320AIC10 (a) Direct Configuration Between C54 and AIC10 DVDD 1 k ...

  • Page 33

    SCLK D15 D14 DCSI Start Bit Device = 0 Address Figure 3–9. Direct Configuration Mode Timing To program control register 1 of device 3, send data in with the following format through DCSI: SB Device Address Register Address 0 0 ...

  • Page 34

    DIN and DOUT Data Format 3.5.1 Primary Serial Communication DIN and DOUT Data Format DIN (15 + 1)-Bit Mode DOUT (15 + 1)-Bit Mode DIN 16-Bit Mode DOUT 16-Bit Mode Figure 3–11. Primary Communication DIN and DOUT Data Format ...

  • Page 35

    Specifications 4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (Unless Otherwise Noted) Supply voltage range Output voltage range, all digital output signals Input voltage range, all digital input signals Case temperature for 10 seconds: ...

  • Page 36

    ADC Path Filter kHz (see Note 2) PARAMETER Filter gain relative to gain at 1020 Hz Filter gain relative to gain at 1020 Hz NOTE 2: The filter gain outside of the passband is measured with ...

  • Page 37

    ADC Channel Characteristics PARAMETER V I(PP) Peak-to-peak input voltage (differential) Dynamic range Intrachannel isolation E G Gain error E O(ADC) ADC converter offset error CMRR Common-mode rejection ratio at INM, INP or AUXM, AUXP Idle channel noise (on-chip reference) ...

  • Page 38

    DAC Signal-to-Distortion + Noise When Load is 600 PARAMETER THD+N THD+N Signal to total harmonic distortion + noise Signal-to-total harmonic distortion + noise NOTE 5: The test condition is the digital equivalent of a 1020-Hz input signal with an ...

  • Page 39

    Power Supply 4.3.10.1 Low-Power Mode (set control register bit PARAMETER P D Power dissipation I DD (analog) I (analog) Supply current Supply current (digital) (digital) Supply current Supply current 4.3.10.2 Normal Operation PARAMETER ...

  • Page 40

    4–6 ...

  • Page 41

    Parameter Measurement Information SCLK FC/FS/FSD t d(3) MCLK SCLK t d(1) FS DOUT DIN Figure 5–2. Serial Communication Timing 2 d(CH–FH) 0.8 V Figure 5–1. FC, FS, and FSD Timing t w( D15 ...

  • Page 42

    AMPLITUDE vs FREQUENCY 1500 2000 2500 3000 f – Frequency – Hz Figure 5–3. FFT–ADC Channel AMPLITUDE vs FREQUENCY 3000 4000 ...

  • Page 43

    Frequency – Hz Figure 5–5. FFT–DAC Channel 0 –30 –60 –90 –120 –150 0 1000 2000 3000 f – Frequency – Hz Figure 5–6. FFT–DAC Channel AMPLITUDE vs ...

  • Page 44

    AMPLITUDE vs FREQUENCY 1500 2000 2500 3000 f – Frequency – Hz Figure 5–7. FFT–ADC Channel AMPLITUDE vs FREQUENCY 3000 4000 ...

  • Page 45

    Frequency – Hz Figure 5–9. FFT–DAC Channel 0 –30 –60 –90 –120 –150 0 1000 2000 3000 f – Frequency – Hz Figure 5–10. FFT–DAC Channel AMPLITUDE vs ...

  • Page 46

    5–6 ...

  • Page 47

    Mechanical Information PFB (S-PQFP-G48) 0, 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. ...

  • Page 48

    ... GQE (S-PBGA-N80) 5,10 SQ 4,90 0,68 0,62 0,35 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar Junior BGA configuration D. Falls within JEDEC MO-225 MicroStar Junior is a trademark of Texas Instruments. 6– 1,00 MAX Seating Plane 0,05 M 0,08 ...

  • Page 49

    Bits D15 through D13 represent the device address in the cascade set by the automatic cascade detection described in Section 2.1.13. In cascading, the master is the device directly connected to the DSP. For example, if there are four devices ...

  • Page 50

    A.1 Control Register ovf – – – – – 1 – – – – 0 – – – – – 1 – – – – 0 – – – – – 1 – – ...

  • Page 51

    A.3 Control Register – – – – – – – – – – – – – – 1 – – – – 0 – – – ...

  • Page 52

    A.4 Control Register ...

  • Page 53

    TLV320AIC10 AURXFP AURXM AURXCP VMID DTXOP DTXIM DTXIP DTXOM OUTP OUTM Figure A–1. Differential Configuration for Hybrid Connection Anti- Sigma- Aliasing PGA Delta Filter ADC V ref Low Sigma- Pass PGA Delta Filter DAC A–5 ...

  • Page 54

    Figure A–2. Single-Ended Configuration of Hybrid Connection A–6 TLV320AIC10 AURXFP AURXM AURXCP Anti- Aliasing Filter VMID DTXOP DTXIM DTXIP DTXOM OUTP PGA OUTM Sigma- PGA Delta ADC Vref Low Sigma- Pass Delta Filter DAC ...

  • Page 55

    PACKAGING INFORMATION (1) Orderable Device Status TLV320AIC10CPFB ACTIVE TLV320AIC10CPFBG4 ACTIVE TLV320AIC10IGQER ACTIVE TLV320AIC10IPFB ACTIVE TLV320AIC10IPFBG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device ...

  • Page 56

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TLV320AIC10IGQER BGA MI GQE CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 80 2500 330.0 12.4 ...

  • Page 57

    Device Package Type TLV320AIC10IGQER BGA MICROSTAR JUNIOR PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) GQE 80 2500 Pack Materials-Page 2 9-Aug-2008 Width (mm) Height (mm) 340.5 333.0 20.6 ...