IC MONO/STER AUD CODEC LP 42-BGA

TLV320AIC3107IYZFR

Manufacturer Part NumberTLV320AIC3107IYZFR
DescriptionIC MONO/STER AUD CODEC LP 42-BGA
ManufacturerTexas Instruments
TypeStereo Audio
TLV320AIC3107IYZFR datasheet
 


Specifications of TLV320AIC3107IYZFR

Data InterfaceI²C, SerialResolution (bits)24 b
Number Of Adcs / Dacs2 / 2Sigma DeltaYes
S/n Ratio, Adcs / Dacs (db) Typ92 / 96Dynamic Range, Adcs / Dacs (db) Typ91 / 92
Voltage - Supply, Analog2.7 V ~ 3.6 VVoltage - Supply, Digital1.525 V ~ 1.95 V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case42-BGALead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-24234-2  
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..............................................................................................................................................
INTEGRATED MONO CLASS-D SPEAKER AMPLIFIER
FEATURES
1
Stereo CODEC with Integrated Mono Class-D
2
Amplifier
High Performance Audio DAC
– 97 dBA Signal-to-Noise Ratio
(Single Ended)
– 16/20/24/32-Bit Data
– Supports Sample Rates From 8 kHz to
96 kHz
– 3D/Bass/Treble/EQ/De-Emphasis Effects
– Flexible Power Saving Modes and
Performance are Available
High Performance Audio ADC
– 92 dBA Signal-to-Noise Ratio
– Supports Rates From 8 kHz to 96 kHz
– Digital Signal Processing and Noise
Filtering Available During Record
Seven Audio Input Pins
– Programmable as 6 Single-Ended or 3 Fully
Differential Inputs
– Capability for Floating Input Configurations
Multiple Audio Output Drivers
– Mono Fully Differential or Stereo
Single-Ended Headphone Drivers
– Single-Ended Stereo Line Outputs
Mono 1W Class-D BTL 8Ω Speaker Driver
Low Power Consumption: 15-mW Stereo
48-kHz Playback With 3.3-V Analog Supply
Ultra-Low Power Mode with Passive Analog
Bypass
Programmable Input/Output Analog Gains
Automatic Gain Control (AGC) for Record
Programmable Microphone Bias Level
Programmable PLL for Flexible Clock
Generation
2
I
C™ Control Bus
Audio Serial Data Bus Supports I
Left/Right-Justified, DSP, and TDM Modes
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Electronics.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LOW-POWER STEREO CODEC WITH
Extensive Modular Power Control
Power Supplies:
– Speaker Amp: 2.7 V–5.5 V
– Analog: 2.7 V–3.6 V.
– Digital Core: 1.525 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
Packages: 5 × 5 mm 40-QFN, 0.4 mm Pitch
3.5 × 3 mm 42-WCSP, 0.5 mm Pitch
APPLICATIONS
Cellular Handsets
Digital Cameras
Portable Media Players
General Portable Audio Equipment
DESCRIPTION
The TLV320AIC3107 is a low power stereo audio
codec with stereo headphone amplifier, and mono
class-D speaker driver, as well as multiple inputs and
outputs programmable in single-ended or fully
differential configurations. Extensive register-based
power control is included, enabling stereo 48-kHz
DAC playback as low as 15 mW from a 3.3-V analog
supply, making it ideal for portable battery-powered
audio and telephony applications.
The record path of the TLV320AIC3107 contains
integrated microphone bias, digitally controlled stereo
microphone preamplifier, and automatic gain control
(AGC), with mix/mux capability among the multiple
analog inputs. Programmable filters are available
during record which can remove audible noise that
can occur during optical zooming in digital cameras.
The playback path includes mix/mux capability from
the stereo DAC and selected inputs, through
programmable volume controls, to the various
outputs.
The TLV320AIC3107 contains three high-power
output drivers as well as two single-ended line output
drivers, and a differential class-D output driver.
2
S,
TLV320AIC3107
SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009
Copyright © 2008–2009, Texas Instruments Incorporated

TLV320AIC3107IYZFR Summary of contents

  • Page 1

    ... DAC and selected inputs, through programmable volume controls, to the various outputs. The TLV320AIC3107 contains three high-power output drivers as well as two single-ended line output drivers, and a differential class-D output driver TLV320AIC3107 SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 2

    ... I/O supply of 1.1 V–3.6 V, and a speaker amplifier supply of 2.7V–5.5V. The device is available in the 5 × 5-mm, 40-pin QFN package, and a 3.5 × 3-mm, 42-lead WCSP package. 2 Submit Documentation Feedback .............................................................................................................................................. 2 C protocol, while the serial audio data bus is programmable for I Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated 2 S, ...

  • Page 3

    ... LEFT _LOP Switching, and Gain/Atten RIGHT _LOP Right Channel DAC SPOP SPOM SWOUTP SWOUTM (1) ORDERING TRANSPORT NUMBER MEDIA, QUANTITY TLV320AIC3107IYZFT Tape and Reel, 250 TLV320AIC3107IYZFR Tape and Reel, 3000 TLV320AIC3107IRSBT Tape and Reel, 250 TLV320AIC3107IRSBR Tape and Reel, 3000 Submit Documentation Feedback ...

  • Page 4

    ... Class-D voltage supply, 2.7 V–5 Class-D (or Bypass SW, WCSP only) positive differential output I Negative Bypass Switch Input Product Folder Link(s): TLV320AIC3107 www.ti.com 2 1 MICDET/LINE1LM SCL A IOVDD SDA B DIN DOUT C BCLK WCLK D GPIO1 MCLK E SPVSS RESET F SPVSS SPVSS Description Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 5

    ... C1 DOUT 39 C3 DVSS 40 B2 IOVDD Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 PIN FUNCTIONS (continued) I/O O Negative Bypass Switch Output tied to SPOM externally O Positive Bypass Switch Output tied to SPOP externally I Positive Bypass Switch Input ...

  • Page 6

    ... T = 85° POWER RATING POWER RATING 600 mW 400 mW 882 mW 588 mW MIN NOM MAX UNIT 2.7 3.3 3.6 1.525 1.8 1.95 1.1 1.8 3.6 2.7 3.6 5.5 0.707 V RMS 10 kΩ –40 85 °C Copyright © 2008–2009, Texas Instruments Incorporated Ω ...

  • Page 7

    ... THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values. Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ...

  • Page 8

    ... Second option Output common mode Third option Fourth option Output volume control max setting Output volume control step size 8 Submit Documentation Feedback .............................................................................................................................................. TEST CONDITIONS Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com MIN TYP MAX UNIT 2 2.3 2.5 2 ...

  • Page 9

    ... IOVDD < 1 Output low level OL V Output high level OH (3) When IOVDD < 1.6V, minimum V is 1.1V. IH Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 TEST CONDITIONS Product Folder Link(s): TLV320AIC3107 TLV320AIC3107 MIN TYP MAX UNIT 2 ...

  • Page 10

    ... ksps, I2S Slave, No signal Stereo LINEIN to stereo LINEOUT, No signal Extra power when PLL enabled All blocks powered down, Headset detection enabled class-D disabled Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com MIN TYP MAX UNIT ...

  • Page 11

    ... DIN hold time h t Rise time r t Fall time f NOTE: All timing specifications are measured at characterization but not tested at final test. Figure 1. I Copyright © 2008–2009, Texas Instruments Incorporated t (WS (DO-BCLK S/LJF/RJF Timing in Master Mode Product Folder Link(s): TLV320AIC3107 TLV320AIC3107 SLOS545C – ...

  • Page 12

    ... NOTE: All timing specifications are measured at characterization but not tested at final test. 12 Submit Documentation Feedback .............................................................................................................................................. t (WS) t (WS (DO-BCLK) d Figure 2. DSP Timing in Master Mode Product Folder Link(s): TLV320AIC3107 www.ti.com t (DI) t (DI IOVDD = 1.1 V IOVDD = 3.3 V MIN MAX MIN MAX Copyright © 2008–2009, Texas Instruments Incorporated T0146-01 UNIT ...

  • Page 13

    ... DIN hold time h t Rise time r t Fall time f NOTE: All timing specifications are measured at characterization but not tested at final test. Figure 3. I Copyright © 2008–2009, Texas Instruments Incorporated t (WS (DO-WS (DO-BCLK S/LJF/RJF Timing in Slave Mode Product Folder Link(s): ...

  • Page 14

    ... NOTE: All timing specifications are measured at characterization but not tested at final test. 14 Submit Documentation Feedback .............................................................................................................................................. t (WS (WS (DO-BCLK) d Figure 4. DSP Timing in Slave Mode Product Folder Link(s): TLV320AIC3107 www.ti.com t (WS (DI) t (DI IOVDD = 1.1 V IOVDD = 3.3 V MIN MAX MIN MAX Copyright © 2008–2009, Texas Instruments Incorporated T0146-02 UNIT ...

  • Page 15

    ... Headphone Out Power - mW Figure 5. MICBIAS VOLTAGE vs SUPPLY VOLTAGE 4 No Load 3.5 PGM = PGM = 2.5 V 2.5 2 1.5 2.7 2.9 3 Supply Voltage - V DD Figure 7. Copyright © 2008–2009, Texas Instruments Incorporated TYPICAL CHARACTERISTICS 45 40 3.6 VDD_CM 1.8_LDAC 3.6 VDD_CM 1.8_RDAC 100 4 3.5 3 2.5 ...

  • Page 16

    ... Figure 9. RIGHT DAC FFT Frequency - kHz Figure 10. LEFT ADC FFT Frequency - kHz Figure 11. Product Folder Link(s): TLV320AIC3107 www.ti.com Load = kHz kHz, s 4096 Samples DRV = 3 Load = kHz kHz DRV = 3 Load = kHz kHz, s 2048 Samples DRV = 3 Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 17

    ... TYPICAL CHARACTERISTICS (continued) 0 -20 -40 -60 -80 -100 -120 -140 -160 Copyright © 2008–2009, Texas Instruments Incorporated RIGHT ADC FFT Frequency - kHz Figure 12. TOTAL HARMONIC DISTORTION vs CLASS-D OUTPUT POWER 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 100 Class-D Output Power - mW Figure 13 ...

  • Page 18

    ... RIGHT _LOP LEFT_LOP 0.47mF Product Folder Link(s): TLV320AIC3107 www.ti.com AVDD (2.7V-3.6V) AVDD_ADC 0.1 mF AVDD_DAC 0.1 mF DRVDD 0 DRVDD IOVDD A (1.1-3.3V) IOVDD 1.525-1.95V DVDD 0.1 mF DVSS D VBAT (2.7-5.5V) SPVDD AVSS_ADC A AVSS_DAC DRVSS SPVSS A Copyright © 2008–2009, Texas Instruments Incorporated 1 mF ...

  • Page 19

    ... Instead, the bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. Copyright © 2008–2009, Texas Instruments Incorporated OVERVIEW ...

  • Page 20

    ... SDA Controlled by Master (S) => SDA Controlled by Slave 2 Figure 16 Write Product Folder Link(s): TLV320AIC3107 www.ti.com 2 C bus has a unique 7-bit address specification for details.) The master D(7) D(0) Slave 8-bit Register Data Slave Ack (M) Ack (S) (S) Copyright © 2008–2009, Texas Instruments Incorporated Stop (M) ...

  • Page 21

    ... By combining this capability with the ability to program at what bit clock in a frame the audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus. Copyright © 2008–2009, Texas Instruments Incorporated RA(7) RA(0) ...

  • Page 22

    ... Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock. 22 Submit Documentation Feedback .............................................................................................................................................. 1/fs Left Channel n− n−1 n−2 LSB n-1 n-2 n-3 Product Folder Link(s): TLV320AIC3107 www.ti.com Right Channel n−2 n− Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 23

    ... In this case, as the offset is programmed from zero to some higher value, both the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in Figure 22 for the two cases. Copyright © 2008–2009, Texas Instruments Incorporated n-1 n-2 n Serial Data Bus Mode Operation ...

  • Page 24

    ... DSP Mode N-1 N N-1 N-2 Right Channel Data Left Channel Data Left Justified Mode 1 0 offset Effect of a Programmed Data Word Offset Product Folder Link(s): TLV320AIC3107 1 0 N-1 N Right Channel Data Figure 23. Copyright © 2008–2009, Texas Instruments Incorporated www.ti.com ...

  • Page 25

    ... NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and Fsref should fall within 39 kHz to 53 kHz. When the PLL is enabled, Fsref = (PLLCLK_IN × K × (2048 × P), where 3,… …, 16 Copyright © 2008–2009, Texas Instruments Incorporated BCLK CLKDIV_IN K*R/P Q=2,3,…..,16,17 2/Q ...

  • Page 26

    ... 1920 1 7 5618 Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com ACHIEVED FSREF % ERROR 44100.00 0.0000 44100.00 0.0000 44100.00 0.0000 44099.71 –0.0007 44100.00 0.0000 44100.00 0.0000 44100.30 0.0007 44100.00 0.0000 ACHIEVED FSREF % ERROR 48000.00 0.0000 48000.00 ...

  • Page 27

    ... N0, N1, and D1. The transfer function of the digital high pass filter is of the form: Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ...

  • Page 28

    ... SW-D1 AGC PGA ADC 0/+59.5dB 0.5dB steps SW-D3 Product Folder Link(s): TLV320AIC3107 www.ti.com DAC Record Path Powered Down SW-D2 Volume DAC Effects Control L DAC Powered Record Path Down SW-D4 Volume DACR Effects Control Copyright © 2008–2009, Texas Instruments Incorporated (1) ...

  • Page 29

    ... Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from +59 steps of 0.5 dB. Copyright © 2008–2009, Texas Instruments Incorporated Table 1. AGC Decay Time Restriction MAXIMUM DECAY TIME (seconds) 1 ...

  • Page 30

    ... Allowed Q values = 12 values where equivalent Fsref can be achieved by turning on PLL (set and and PLL enabled 10, 14 (set and and PLL enabled) 30 Submit Documentation Feedback .............................................................................................................................................. Decay Time Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com Target Level Attack Time ...

  • Page 31

    ... N3, N4, N5, D4, and D5. The RB1 and RB2 filters refer to the first and second right-channel biquad filters, respectively. Figure 26. Structure of the Digital Effects Processing for Independent Channel Processing Copyright © 2008–2009, Texas Instruments Incorporated N0 16950 ...

  • Page 32

    ... By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be entirely avoided. 32 Submit Documentation Feedback .............................................................................................................................................. 32131 –27034 + + + LB1 Atten – Product Folder Link(s): TLV320AIC3107 www.ti.com –31506 26461 LB2 To Left Channel To Right Channel RB2 B0155-01 Copyright © 2008–2009, Texas Instruments Incorporated Table 3 ...

  • Page 33

    ... Page 0, Register 109 bits D7-D6. The lowest DAC current setting is the default, and the dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic range 1.5dB. Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Product Folder Link(s): ...

  • Page 34

    ... Table 4. Appropriate Settings RECOMMENDED AVDD_DAC, DRVDD 2.7 V – 3.6 V 3.0 V – 3.6 V 3.3 V – 3.6 V 3.6 V Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com RECOMMENDED DVDD 1.525 V – 1.95 V 1.65 V – 1.95 V 1.8 V – 1.95 V 1.95 V ...

  • Page 35

    ... LINE2RP/ LINE 2LM VCM LINE1RM VCM VCM VCM Copyright © 2008–2009, Texas Instruments Incorporated 0dB to -18dB in 0.5dB Steps 0dB, -6dB, or -12dB 0dB to -18dB in 0.5dB Steps 0dB to -18dB in 0.5dB Steps 0dB to -18dB in 0.5dB Steps 0dB to -18dB in 0.5dB Steps For LINE1L Single-Ended 0dB to -18dB in 0 ...

  • Page 36

    ... Steps For LINE1L Single-Ended 0dB to -18dB in 0.5dB Steps For MIC3L 0dB to -18dB in 0.5dB Steps For MIC3R 0dB to -18dB in 0.5dB Steps Figure 29. Right Signal Path Product Folder Link(s): TLV320AIC3107 www.ti.com Right ADC PDWN Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 37

    ... Three fully-differential analog inputs can similarly be mixed into the right ADC PGA as well, consisting of LINE1RP-LINE1RM, LINE2RP-LINE2RM, and LINE1LP-LINE1LM. Note that it is not necessary to mix all three fully-differential signals if this is not desired – unnecessary inputs can simply be muted using the input level control registers. Copyright © 2008–2009, Texas Instruments Incorporated (differential). pp Product Folder Link(s): ...

  • Page 38

    ... LINE2RP-LINE2RM to the output stage directly single-ended configuration, the device can pass the signal LINE2LP and LINE2RP to the output stage directly. 38 Submit Documentation Feedback .............................................................................................................................................. GAIN=0, -1.5, -3, .., -12dB,MUTE GAIN=0, -6, -12dB, MUTE GAIN=0, -1.5, -3, .., -12dB,MUTE GAIN=0, -1.5, -3, .., -12dB,MUTE Product Folder Link(s): TLV320AIC3107 www.ti.com TO LEFT ADC PGA Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 39

    ... In general, connecting two switches to the same output pin should be avoided, as this error will short two input signals together, and can cause distortion of the signal as the two signal are in contention, and poor frequency response can occur. Copyright © 2008–2009, Texas Instruments Incorporated Passive Analog Bypass Mode Configuration. Programming this mode is done Product Folder Link(s): ...

  • Page 40

    ... LINE1RM LINE2RP LINE2RM Product Folder Link(s): TLV320AIC3107 www.ti.com To Internal Class-D Plus Input SW-L2 LINE2LP SW-L1 LINE1LP SW-L0 LEFT_LOP SW-L3 SW-L4 LINE1LM SW-L5 LINE2LM To Internal Class-D Minus Input (LEFT_LOM) SW-R2 LINE2RP SW-R1 LINE1RP SW-R0 RIGHT_LOP Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 41

    ... PGA_L PGA_R DAC_L1 DAC_R1 DAC_L3 LINE2L LINE2R PGA_L PGA_R DAC_L1 DAC_R1 DAC_R3 Figure 33. Architecture of the Output Stage Leading to the Line Output Drivers Copyright © 2008–2009, Texas Instruments Incorporated DAC_L1 DAC_L DAC_L2 DAC_L3 STEREO AUDIO DAC_R1 DAC_R DAC DAC_R2 DAC_R3 VOLUME ...

  • Page 42

    ... VCM level, for a pseudo-differential stereo output 42 Submit Documentation Feedback .............................................................................................................................................. 0dB to -78dB 0dB to -78dB 0dB to -78dB 0dB to -78dB 0dB to -78dB 0dB to -78dB Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com + Figure 26 and Figure 16 ...

  • Page 43

    ... However, this option provides the fastest method for transitioning the drivers from powerdown to full power operation without any output artifact introduced. Copyright © 2008–2009, Texas Instruments Incorporated Volume 0dB to +9dB, mute ...

  • Page 44

    ... Submit Documentation Feedback .............................................................................................................................................. MICBIAS MICDET MIC3(L/R) HPLOUT HPROUT HPCOM Output Connection Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com AVDD To Detection block To detection block 1.35 Figure ...

  • Page 45

    ... The registers that control this functionality are in Page-0/Reg-38/Bit-D2-D1. This switch closes when jack is removed Figure 38. Configuration of Device for Jack Detection Using a Fully Differential Stereo Headphone Output Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 MICBIAS MICDET ...

  • Page 46

    ... LEFT_LOM - 6dB steps Power Supplies Bypass Switch (R73-D1) Bypass Switch Bootstrap Clock Enable (R73-D0 Product Folder Link(s): TLV320AIC3107 www.ti.com Figure 39. The 32. A register (73) is used to enable the 26 SPOP 23 SPOM 29 SWOUTP 28 SWOUTM Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 47

    ... D6–D0 W 0000000 Copyright © 2008–2009, Texas Instruments Incorporated Page Select Register DESCRIPTION Reserved, write only zeros to these register bits Page Select Bit Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a one to this bit sets Page-1 as the active page for following register accesses recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes ...

  • Page 48

    ... PLL Programming Register A DESCRIPTION PLL Control Bit 0: PLL is disabled 1: PLL is enabled PLL Q Value 0000 0001 : 0010 : 0011 : 0100 : … 1110 1111 PLL P Value 000 001 010 011 100 101 110 111 Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 49

    ... D5 R/W 0 D4–D3 R/W 00 D2–D1 R R/W 0 Copyright © 2008–2009, Texas Instruments Incorporated PLL Programming Register B DESCRIPTION PLL J Value 000000: Reserved, do not write this sequence 000001 000010 000011 … 111110 111111 Reserved, write only zeros to these bits PLL Programming Register C DESCRIPTION zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6 ...

  • Page 50

    ... Re-Sync is done without soft-muting the channel. (ADC/DAC) 1: Re-Sync is done by internally soft-muting the channel. (ADC/DAC) 50 Submit Documentation Feedback .............................................................................................................................................. Audio Serial Data Interface Control Register A DESCRIPTION Audio Serial Data Interface Control Register B DESCRIPTION 2 S mode Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com ...

  • Page 51

    ... R 0 D3–D0 R/W 0001 Copyright © 2008–2009, Texas Instruments Incorporated Audio Serial Data Interface Control Register C DESCRIPTION Audio Serial Data Word Offset Control This register determines where valid data is placed or expected in each frame, by controlling the offset from beginning of the frame where valid data begins. The offset is measured from the rising edge of word clock when in DSP mode ...

  • Page 52

    ... Reserved, do not write this bit sequence to these register bits. Headset Glitch Suppression Debounce Control for Button Press 00: Debounce = 0msec 01: Debounce = 8msec(sampled with 1ms clock) 10: Debounce = 16msec(sampled with 2ms clock) 11: Debounce = 32msec(sampled with 4ms clock) Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 53

    ... VALUE D7 R/W 1 D6-D0 R/W 0000000 Copyright © 2008–2009, Texas Instruments Incorporated Headset / Button Press Detection Register B DESCRIPTION Driver Capacitive Coupling 0: Programs high-power outputs for capless driver configuration 1: Programs high-power outputs for ac-coupled driver configuration Stereo Output Driver Configuration A Note: do not set bits D6 and D3 both high at the same time. ...

  • Page 54

    ... Input level control gain = –10.5 dB 1000: Input level control gain = –12.0 dB 1001–1110: Reserved. Do not write these sequences to these register bits 1111: MIC3R is not connected to right ADC PGA Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 55

    ... D1- (1) LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels. Copyright © 2008–2009, Texas Instruments Incorporated LINE1L to Left ADC Control Register DESCRIPTION LINE1L Single-Ended vs Fully Differential Control If LINE1L is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode) ...

  • Page 56

    ... Right ADC channel is powered up Right ADC PGA Soft-Stepping Control 00: Right ADC PGA soft-stepping at once per Fs 01: Right ADC PGA soft-stepping at once per two Fs 10-11: Right ADC PGA soft-stepping is disabled Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 57

    ... D7–D6 R/W 00 D5–D0 R/W 000000 Copyright © 2008–2009, Texas Instruments Incorporated LINE2R to Right ADC Control Register DESCRIPTION LINE1L to Right ADC Control Register DESCRIPTION LINE1L Single-Ended vs Fully Differential Control If LINE1L is selected to both left and right ADC channels, both connections must use the same configuration (single-ended or fully differential mode) ...

  • Page 58

    ... Left AGC noise threshold = –86 dB 11110: Left AGC noise threshold = –88 dB 11111: Left AGC noise threshold = –90 dB Left AGC Clip Stepping Control 0: Left AGC clip stepping disabled 1: Left AGC clip stepping enabled Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 59

    ... R/W 00 D5–D1 R/W 00000 D0 R/W 0 Copyright © 2008–2009, Texas Instruments Incorporated Right AGC Control Register A DESCRIPTION Right AGC Enable 0: Right AGC is disabled 1: Right AGC is enabled Right AGC Target Level 000: Right AGC target level = –5.5 dB 001: Right AGC target level = –8 dB 010: Right AGC target level = – ...

  • Page 60

    ... Debounce = 0-msec 001: Debounce = 0.5-msec 010: Debounce = 1-msec 011: Debounce = 2-msec 100: Debounce = 4-msec 101: Debounce = 8-msec 110: Debounce = 16-msec 111: Debounce = 32-msec Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 61

    ... Copyright © 2008–2009, Texas Instruments Incorporated Right AGC Noise Gate Debounce Register DESCRIPTION Right AGC Noise Detection Debounce Control (1) These times will not be accurate when double rate audio mode is enabled. 00000: Debounce = 0-msec 00001: Debounce = 0.5-msec 00010: Debounce = 1-msec 00011: Debounce = 2-msec ...

  • Page 62

    ... Reserved. Do not write this sequence to these register bits. Reserved. Write only zeros to these register bits. High Power Output Driver Control Register DESCRIPTION Reserved Register DESCRIPTION High Power Output Stage Control Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 63

    ... Gain = –0.5 dB 0000010: Gain = –1.0 dB … 1111101: Gain = –62.5 dB 1111110: Gain = –63.0 dB 1111111: Gain = –63.5 dB Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 DAC Output Switching Control Register DESCRIPTION Output Driver Pop Reduction Register DESCRIPTION ...

  • Page 64

    ... Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 65

    ... PGA_R Output Routing Control 0: PGA_R is not routed to HPLOUT 1: PGA_R is routed to HPLOUT D6-D0 R/W 0000000 PGA_R to HPLOUT Analog Volume Control For 7-bit register setting versus analog gain values, see Copyright © 2008–2009, Texas Instruments Incorporated Analog Gain Gain Setting (dB) 57 -28 -29.1 ...

  • Page 66

    ... DESCRIPTION HPLOUT Output Level Control Register DESCRIPTION LINE2L to HPCOM Volume Control Register DESCRIPTION PGA_L to HPCOM Volume Control Register DESCRIPTION DAC_L1 to HPCOM Volume Control Register DESCRIPTION Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com Table 5 Table 5 Table 5 Table 5 ...

  • Page 67

    ... R/W 0000000 LINE2L to HPROUT Analog Volume Control For 7-bit register setting versus analog gain values, see Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 LINE2R to HPCOM Volume Control Register DESCRIPTION PGA_R to HPCOM Volume Control Register ...

  • Page 68

    ... DAC_L1 to HPROUT Volume Control Register DESCRIPTION LINE2R to HPROUT Volume Control Register DESCRIPTION PGA_R to HPROUT Volume Control Register DESCRIPTION DAC_R1 to HPROUT Volume Control Register DESCRIPTION Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com Table 5 Table 5 Table 5 Table 5 Table 5 ...

  • Page 69

    ... Reserved. Do not write to this register. BIT READ/ RESET WRITE VALUE D7–D R 00000000 Reserved. Do not write to this register. 0 Copyright © 2008–2009, Texas Instruments Incorporated HPROUT Output Level Control Register DESCRIPTION Page 0 / Register 66: Reserved DESCRIPTION Page 0 / Register 67: Reserved DESCRIPTION Page 0 / Register 68: ...

  • Page 70

    ... D7–D0 R 00000000 Reserved. Do not write to this register. 70 Submit Documentation Feedback .............................................................................................................................................. Page 0 / Register 72: Reserved DESCRIPTION Class-D and Bypass Switch Control Register DESCRIPTION Page 0 / Register 74: Reserved DESCRIPTION Page 0 / Register 75: Reserved DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 71

    ... LINE2L Output Routing Control 0: LINE2L is not routed to LEFT_LOP 1: LINE2L is routed to LEFT_LOP D6-D0 R/W 0000000 LINE2L to LEFT_LOP Analog Volume Control For 7-bit register setting versus analog gain values, see Copyright © 2008–2009, Texas Instruments Incorporated DESCRIPTION Page 0 / Register 77: Reserved DESCRIPTION Page 0 / Register 78: Reserved DESCRIPTION ...

  • Page 72

    ... DAC_L1 to LEFT_LOP Volume Control Register DESCRIPTION LINE2R to LEFT_LOP Volume Control Register DESCRIPTION PGA_R to LEFT_LOP Volume Control Register DESCRIPTION Table 5 DAC_R1 to LEFT_LOP Volume Control Register DESCRIPTION Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com Table 5 Table 5 Table 5 Table 5 ...

  • Page 73

    ... R/W 0000000 LINE2R to RIGHT_LOP Analog Volume Control For 7-bit register setting versus analog gain values, see Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 LEFT_LOP Output Level Control Register DESCRIPTION LINE2L to RIGHT_LOP Volume Control Register ...

  • Page 74

    ... RIGHT_LOP is not fully powered up 1: RIGHT_LOP is fully powered up 74 Submit Documentation Feedback .............................................................................................................................................. PGA_R to RIGHT_LOP Volume Control Register DESCRIPTION DAC_R1 to RIGHT_LOP Volume Control Register DESCRIPTION RIGHT_LOP Output Level Control Register DESCRIPTION Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com Table 5 Table 5 ...

  • Page 75

    ... HPCOM is not fully powered up 1: HPCOM is fully powered up D2- Reserved. Do not write to these register bits. Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Module Power Status Register DESCRIPTION Output Driver Short Circuit Detection Status Register DESCRIPTION ...

  • Page 76

    ... Right ADC Signal Power Lower than Noise Threshold for Right AGC (1) This bit is a sticky bit, cleared only when page 0, register 14 is read. 76 Submit Documentation Feedback .............................................................................................................................................. Sticky Interrupt Flags Register DESCRIPTION Real-time Interrupt Flags Register DESCRIPTION (1) Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com ...

  • Page 77

    ... A logic-high level is input to GPIO1 D0 R/W 0 GPIO1 General Purpose Output Value 0: GPIO1 outputs a logic-low level 1: GPIO1 outputs a logic-high level Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 GPIO1 Control Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 TLV320AIC3107 ...

  • Page 78

    ... Page 0 / Register 99: Reserved DESCRIPTION Page 0 / Register 100: Reserved DESCRIPTION CODEC CLKIN Source Selection Register DESCRIPTION Clock Generation Control Register DESCRIPTION Left AGC New Programmable Attack Time Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 79

    ... Multiplication factor for the baseline AGC Attack time = 128 D1-D0 R/W 00 Reserved. Write only zero to these register bits. Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 Left AGC Programmable Decay Time Register DESCRIPTION Right AGC Programmable Attack Time Register ...

  • Page 80

    ... C bus error is detected. This bit is cleared by reading this register. 80 Submit Documentation Feedback .............................................................................................................................................. Right AGC New Programmable Decay Time Register DESCRIPTION DESCRIPTION 2 C bus error, and clears the bus error condition bus error. Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3107 www.ti.com ( Bus Condition Register ...

  • Page 81

    ... This register has the same functionality on page-0 and page-1. Copyright © 2008–2009, Texas Instruments Incorporated SLOS545C – NOVEMBER 2008 – REVISED MARCH 2009 ...

  • Page 82

    ... Left Channel Audio Effects Filter N1 Coefficient LSB Register DESCRIPTION Left Channel Audio Effects Filter N2 Coefficient MSB Register DESCRIPTION Left Channel Audio Effects Filter N2 Coefficient LSB DESCRIPTION Left Channel Audio Effects Filter N3 Coefficient MSB Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com (1) Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 83

    ... The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Copyright © 2008–2009, Texas Instruments Incorporated Left Channel Audio Effects Filter N3 Coefficient LSB Register DESCRIPTION ...

  • Page 84

    ... Left Channel Audio Effects Filter D5 Coefficient LSB Register DESCRIPTION Left Channel De-emphasis Filter N0 Coefficient MSB Register DESCRIPTION Left Channel De-emphasis Filter N0 Coefficient LSB Register DESCRIPTION Left Channel De-emphasis Filter N1 Coefficient MSB Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 85

    ... Right Channel Audio Effects Filter N2 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Copyright © 2008–2009, Texas Instruments Incorporated Left Channel De-emphasis Filter N1 Coefficient LSB Register DESCRIPTION ...

  • Page 86

    ... Right Channel Audio Effects Filter N4 Coefficient LSB Register DESCRIPTION Right Channel Audio Effects Filter N5 Coefficient MSB Register DESCRIPTION Right Channel Audio Effects Filter N5 Coefficient LSB Register DESCRIPTION Right Channel Audio Effects Filter D1 Coefficient MSB Register DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 87

    ... Right Channel De-emphasis Filter N0 Coefficient MSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from –32768 to +32767. Copyright © 2008–2009, Texas Instruments Incorporated Right Channel Audio Effects Filter D1 Coefficient LSB Register DESCRIPTION ...

  • Page 88

    ... Right Channel De-emphasis Filter D1 Coefficient MSB Register DESCRIPTION Right Channel De-emphasis Filter D1 Coefficient LSB Register DESCRIPTION 3-D Attenuation Coefficient MSB Register DESCRIPTION 3-D Attenuation Coefficient LSB Register DESCRIPTION Reserved Registers DESCRIPTION Product Folder Link(s): TLV320AIC3107 www.ti.com Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 89

    ... Right Channel ADC High Pass Filter N0 Coefficient LSB The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s complement integer, with possible values ranging from -32768 to +32767. Copyright © 2008–2009, Texas Instruments Incorporated Left Channel ADC High Pass Filter N0 Coefficient MSB Register DESCRIPTION ...

  • Page 90

    ... Right Channel ADC High Pass Filter D1 Coefficient MSB Register DESCRIPTION Right Channel ADC High Pass Filter D1 Coefficient LSB Register DESCRIPTION Reserved Registers DESCRIPTION YZF Package Dimensions D Min = 3503 m Max = 3563 m Product Folder Link(s): TLV320AIC3107 www.ti.com E Min = 3316 m Max = 3376 m Copyright © 2008–2009, Texas Instruments Incorporated ...

  • Page 91

    LINE2LP LINE2L Bypass Path Control (R40) 7 LINE2LP LINE2LP LINE2L 8 LINE2LM LINE2RP/LINE2LM Gain: (R20 -12 dB 6.0dB steps LINE2LM PLL Regs = (R3-R6) Left AGC Control: (R26-R28,R32,R34, MIC3L MIC3L 6 MIC3L/LINE1RM R103-R104) Gain: (R17 -12 ...

  • Page 92

    ... PACKAGING INFORMATION (1) Orderable Device Status TLV320AIC3107IRSBR ACTIVE TLV320AIC3107IRSBT ACTIVE TLV320AIC3107IYZFR ACTIVE TLV320AIC3107IYZFT ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 93

    TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TLV320AIC3107IRSBR WQFN RSB TLV320AIC3107IRSBT WQFN RSB PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 40 3000 330.0 12.4 5.3 40 ...

  • Page 94

    Device Package Type TLV320AIC3107IRSBR WQFN TLV320AIC3107IRSBT WQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RSB 40 3000 RSB 40 250 Pack Materials-Page 2 8-Dec-2009 Width (mm) Height (mm) 346.0 346.0 29.0 190.5 212.7 ...

  • Page 95

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  • Page 98

    D: Max = 3563 mm, Min = 3503 mm E: Max = 3376 mm, Min = 3316 mm ...

  • Page 99

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...