AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 16

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
dependent; depending upon the sequence in which the hardware
resources are powered down, the savings may be more or less
than the typical numbers given.
Mode Changing
In general, there are very few restrictions with respect to chang-
ing the operating mode of the AD1843. Because of the advanced
Continuous Time Oversampling technology, the waiting period
associated with changes to the sample rate of the data converters
(“Mode Change Enable” resynchronization delay) is eliminated.
The only waiting periods associated with the AD1843 occur at
start-up, and are documented in the “START-UP SEQUENCE”
section below. Following the start-up sequence, the sample rate
of the four data conversion resources on the AD1843 may be
changed at any time, on-the-fly (presuming that they are
enabled). All gain, mute and attenuation settings of enabled
resources may also be changed at any time.
Channel Synchronization
If multiple AD1843s are used in a daisy-chained system, and it
is desired to synchronize data conversion activity among the
multiple codecs, the clock generator blocks of the AD1843s
must be enabled on the same frame (see step 5 in the “START-
UP SEQUENCE” section below).
A DAC channel does not actually start processing samples until
the first rising edge of the conversion clock (CONV pin) after
the sixth rising edge of frame sync (SDFS pin) after the channel
is enabled (via a write to DA1EN or DA2EN in Control Regis-
ter Address 27). The wait until the sixth rising edge of frame
sync is necessary to allow the four deep DAC FIFO to be filled
before conversion commences. The subsequent wait until the
rising edge of the conversion clock is necessary to synchronize
the serial interface based DAC channel enable command with a
conversion clock that is potentially already running (which is
particularly likely if the SYNC pin inputs and lock mode are
in use).
The ADC channels behave very similarly to the DAC channels.
An ADC channel does not actually start taking samples until the
first rising edge of the conversion clock (CONV pin) after the
sixth rising edge of frame sync (SDFS pin) after the channel is
enabled (via a write to ADLEN or ADREN in Control Register
Address 27). The wait until the sixth rising edge of frame sync is
present so that the ADC startup is similar to that of the DAC
startup, as well as to allow some time for stale ADC data inside
the AD1843 to be cleared. The subsequent wait until the rising
edge of the conversion clock is necessary to synchronize the
serial interface based ADC channel enable command with a
conversion clock that it potentially already running (which is par-
ticularly likely if the SYNC pin inputs and lock mode are in use).
Supported Conversion Rates
With all conversion channels operating (i.e., ADC left, ADC
right, DAC1 and DAC2), the AD1843 is able to support sam-
pling rates up to 49 kHz, which 2.1% higher than the nominal
maximum audio standard of 48 kHz, to accommodate timebase
drift while configured in slave mode. If either one DAC (i.e.,
either DAC1 or DAC2) or both ADC channels (i.e., ADC left
and ADC right) are shut down, then the AD1843 can support
sampling up to 54 kHz on all channels of the remaining conver-
–16–
sion resources, as long as the DFREE bit (Control Register Ad-
dress 27) is asserted (i.e., set to “1”). If DFREE is not asserted,
then the maximum sampling rate for the remaining conversion
resources is 49 kHz.
Digital Filter Selection
The operative digital filter modes for the four conversion re-
sources on the AD1843 SoundComm are programmed using
Control Register Address 25. ADLFLT (Bit 0) selects the digi-
tal filter mode for the ADC left channel and ADRFLT (Bit 1)
selects the digital filter mode for the ADC right channel. Note
that these bits also establish the full-scale input voltage range for
these channels as well. DA1FLT (Bit 8) selects the DAC1 digi-
tal filter mode, and DA2FLT (Bit 9) selects the DAC2 digital
filter mode. Note that these bits also establish the full-scale out-
put voltage for these channels as well.
The three digital filter modes are audio, modem and resampler.
The specifications for these modes are given in the description
of Control Register Address 25, as well as in the “SPECIFICA-
TIONS” section of this data sheet. The specifications have been
made to satisfy the demands of the applications which the
AD1843 can serve. The audio mode provides decimation and
interpolation characteristics sufficient for high quality cap-
ture and playback of material from 20 Hz to 20 kHz. The mo-
dem mode provides characteristics sufficient for modulation
standards up to V.34 quality. The resampling mode provides
optimal characteristics for high quality sample rate conversion.
While in the resampling mode, all images in the resampled data
stream (including those in the transition band) are attenuated to
below the quantization noise floor. Note that the maximum
sample rate for modem mode is 24 kHz.
Digital Resampling
Digital resampling is best achieved by routing the digital output
of one of the DACs back to the digital input of one of the
ADCs. This bypasses the analog portion of the DAC and ADC,
eliminating their noise and signal delay contributions. This fea-
ture is enabled by bits DAADR1:0 (Digital ADC Right Channel
Source Select) and DAADL1:0 (Digital ADC Left Channel
Source Select) in Control Register Address 25.
If the “Digital Resampler Filter Mode” (DRSFLT bit = “1,”
Control Register Address 25) is enabled, the DAC2 pair is sacri-
ficed, but the remaining four channels (ADC left and right,
DAC1 left and right) can still be used in any way they could
have been when not in “Digital Resampler Filter Mode.” When
in this mode, internal AD1843 hardware normally devoted to
DAC2 is reallocated to the other four channels, allowing these
channels to realize superior digital filtering. Note that the
AD1843 DOES NOT actually have to be in digital resampler
filter mode to perform digital resampling, however the superior
digital filters in this mode allow for a much higher quality digital
resampling.
Using the AD1843 in a Modem Application
The AD1843 analog performance is sufficient to support the
modem Analog Front End (AFE) function, for data modulation
standards up to and including the 28.8 kbps V.34 ITU stan-
dard. The data pump function is performed in a companion
DSP, such as the ADSP-2181, for which several V.34 algo-
rithms (from third party Independent Algorithm Vendors) exist.
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