AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 31

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
res
LX2MM
LX2M4:0
RX2MM
RX2M4:0
res
LX3MM
LX3M4:0
Address 5
Address 6
LX2MM
RX2MM
LX3MM
RX3MM
Data 15
Data 15
Data 7
Data 7
Left Auxiliary 2 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Left Auxiliary 2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Right Auxiliary 2 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Right Auxiliary 2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register Ad-
dress 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or the
ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
Left Auxiliary 3 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Left Auxiliary 3 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written
to when: the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in
Control Register Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to
analog mix disabled), or the ANAEN bit (analog channels powered down) in Control Register Address 27 is
reset to “0.”
Data 14
Data 14
Data 6
Data 6
res
res
res
res
Data 13
Data 13
Data 5
Data 5
res
res
res
res
Mix Control—Auxiliary 2 to Mixer
Mix Control—Auxiliary 3 to Mixer
Data 12
Data 12
LX2M4
RX2M4
LX3M4
RX3M4
Data 4
Data 4
–31–
Data 11
Data 11
LX2M3
RX2M3
LX3M3
RX3M3
Data 3
Data 3
Data 10
Data 10
LX2M2
RX2M2
LX3M2
RX3M2
Data 2
Data 2
LX2M1
RX2M1
LX3M1
RX3M1
Data 9
Data 1
Data 9
Data 1
LX2M0
RX2M0
LX3M0
RX3M0
Data 8
Data 0
Data 8
Data 0
AD1843