AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 34

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

AD1843
LDA1G5:0
RDA1GM
RDA1G5:0
res
LDA2GM
LDA2G5:0
RDA2GM
RDA2G5:0
res
Address 10
LDA2GM
RDA2GM
Data 15
Data 7
Left DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the
Right DAC1 Analog Mute
Right DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Left DAC2 Analog Mute
Left DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-
Right DAC2 Analog Mute
Right DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
implementation of the attenuation is mixed analog and digital.
0 00000 =
0 01000 =
0 11111 =
1 00000 =
1 11111 =
0 = Right DAC1 Enabled
1 = Right DAC1 Muted
implementation of the attenuation is mixed analog and digital.
0 00000 =
0 01000 =
0 11111 =
1 00000 =
1 11111 =
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”
(analog channels powered down); or when the DA1EN bit in Control Register Address 27 is reset to “0” (DAC1
disabled).
0 = Left DAC2 Enabled
1 = Left DAC2 Muted
mentation of the attenuation is mixed analog and digital.
0 00000 =
0 01000 =
0 11111 =
1 00000 =
1 11111 =
0 = Right DAC2 Enabled
1 = Right DAC2 Muted
mentation of the attenuation is mixed analog and digital.
0 00000 =
0 01000 =
0 11111 =
1 00000 =
1 11111 =
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”
(analog channels powered down); or when the DA2EN bit in Control Register Address 27 is reset to “0” (DAC2
disabled).
Data 14
Data 6
res
res
+12.0 dB:
0.0 dB:
–34.5 dB:
–36.0 dB:
–82.5 dB:
+12.0 dB:
0.0 dB:
–34.5 dB:
–36.0 dB:
–82.5 dB:
+12.0 dB:
0.0 dB:
–34.5 dB:
–36.0 dB:
–82.5 dB:
+12.0 dB:
0.0 dB:
–34.5 dB:
–36.0 dB:
–82.5 dB:
Output Control—DAC2 Analog Gain/Attenuation
LDA2G5
RDA2G5
Data 13
Data 5
+12.0 dB Analog,
+0.0 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
+12.0 dB Analog,
+0.0 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
+12.0 dB Analog,
+0.0 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
+12.0 dB Analog,
+0.0 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
–34.5 dB Analog,
LDA2G4
RDA2G4
Data 12
Data 4
–34–
LDA2G3
RDA2G3
Data 11
Data 3
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
LDA2G2
RDA2G2
Data 10
Data 2
LDA2G1
RDA2G1
Data 9
Data 1
LDA2G0
RDA2G0
Data 8
Data 0
REV. 0