AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 41

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
NTSC
Divisor
1
2
3
4
5
6
7
8
*When C2M6:4 = “100,” base frequency is 48,000 Hz only if NTSC sync rate is increased by 1001/1000, or is exactly 15.750 kHz.
PAL
Divisor
1
2
3
4
5
6
7
8
(C2M7:4) must be programmed to the Conversion clock rate established using Control Register Address 20 and the
C2X8/7 bit. If the actual Conversion clock differs from the value selected by C2M7:4, then the resultant Bit clock will
be different from the rate selected by the ratio of the C2M7:4 selected rate to the Control Register Address 20 plus
the C2X8/7 bit actual rate.
C2M3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
*Bit clock frequencies listed will be increased by 200 Hz if C2P200 is set to “1.”
When C2M7:4 is programmed to “1111” and C2M3:0 is programmed to “1111,” the Bit clock rate will be 128 times
the Conversion rate.
When in Video Lock Mode (C2REF and C2VID are both set to “1”):
Bits C2M7:0 select the Conversion clock rate. The most significant bit (C2M7) must be set to indicate the type of
video lock, either NTSC or PAL. For an NTSC lock, C2M7 must be reset to “0,” and the SYNC2 pin must receive
the NTSC sync frequency (525 lines/frame 30 Hz
must be set to “1,” and the SYNC2 pin must receive the PAL sync frequency (625 lines/frame 25 Hz frame rate
15.625 kHz). The next three most significant bits (C2M6:4) select a desired base Conversion clock rate, and the least
significant four bits (C2M3:0) select a divisor. The Conversion clock created by Clock Generator 2 will be the base
divided by the divisor. The following tables list the possible choices for base and divisor.
Initial default state after reset: 0000 0000 1111 1111 (00FF hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; or when the PWRDWN pin is asserted LO.
(C2M7 = “0”):
(C2M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
(C2M7 = “1”):
(C2M3:0)
(0000)
(0001)
(0010)
(0011)
(0100)
(0101)
(0110)
(0111)
Bit Clock Frequency*
2,400
4,800
7,200
9,600
12,000
14,400
16,800
19,200
21,600
24,000
26,400
28,800
Reserved
Reserved
Reserved
See Below
Base Frequency In Hz (C2M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Base Frequency In Hz (C2M6:4)
48,000
(000)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hertz
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
32,000
(001)
Yes
Yes
No
Yes
Yes
No
No
No
–41–
C2M7:4
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1000/1001 frame rate
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
44,100
(010)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Conversion (Sample) Rate
7,200
9,000
9,600
12,000
44,100
No
No
No
44,100
No
No
No
No
7,200
8,400
9,000
9,600
11,200
12,000
12,800
Reserved
Reserved
Reserved
Reserved
See Below
(011)
Yes
Yes
Yes
Yes
No
(011)
Yes
Yes
Yes
Yes
15.734 kHz). For a PAL lock, C2M7
8/7
8/7
8/7
8/7
2/3
2/3
Hertz
48,000*
(100)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
AD1843
44,056
(101)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes