AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 55

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
8. Configure conversion resources while they are enabled.
The AD1843 Start-Up Sequence state diagram is shown in
Figure 17.
APPLICATIONS CIRCUITS
The AD1843 SoundComm Codec has been designed to require
a minimum of external circuitry. The recommended circuits are
shown in Figures 18 through 34. Analog Devices estimates that
the total cost of all the components shown in these Figures (in-
cluding the crystal but not including the DAA) to be less than
$6 in 10,000 piece quantities.
Industry-standard compact disc “line-levels” are 2 V rms cen-
tered around analog ground. (For other audio equipment, “line
level” is much more loosely defined.) The AD1843 SoundComm
Codec is a +5 V analog supply powered device. Nominal line
level voltage swings for the AD1843 are defined to be 1 V rms
(ADRFLT and ADLFLT = 0) for a sine wave ADC input and
0.707 V rms for a sine wave DAC output (DA2FLT = 0). Thus,
2 V rms input analog signals must be attenuated and either cen-
tered around the reference voltage intermediate between 0 V
and +5 V or ac-coupled. The CMOUT pin will be at this inter-
mediate voltage, nominally 2.25 V. It has limited drive but can
be used as a voltage datum to an op amp input. CMOUT load-
ing should be minimized to limit any audible clicks and pops.
Note that dc-coupled inputs are not recommended, as they pro-
vide no performance benefits with the AD1843 architecture.
Furthermore, dc offsets on inputs create the potential for clicks
when changing the input mix gain/attenuation/mute.
The RESET pin must be asserted at or shortly after power up in
order to initialize the AD1843 Control Registers to their default
states. If the AD1843 will not be used immediately, and if it is
desired to utilize the mono input to mono output feedthrough
feature, it is essential that the mono output is ac-coupled to pre-
vent audible pops and clicks. It is recommended that all outputs
are ac coupled, as standing current in output loads or in the
voltage reference will contribute to audible pops and clicks.
in which the valid flag is first asserted, and continues to be
asserted in future frames, depends on how the AD1843 is
configured, i.e., the sample rates selected, the frame size
selected, and how the shared digital resources within the
AD1843 are internally allocated to process all conversion
channels. Note that because of this, two ADCs which are
enabled during the same frame and share the same sample
rate clock, will not necessarily transmit data during the same
frames thereafter, even though their analog inputs will always
be sampled at the same instant in time. The two ADCs will
transmit data during the same frame if ADTLK (Control
Register Address 26, Bit 4) is set HI. See the description of
the ADTLK bit for restrictions.
If mixing is enabled, either a mix from DAC2 to DAC1 or a
mix from an ADC input to a DAC output, then the mix will
begin during the same TDM frame that it is enabled.
Once enabled, DAC output gain/attenuation levels may be
changed using Control Register Addresses 3 through 10.
These registers are forced to their default of full attenuation
whenever the resource they control is either in standby or
completely powered down. Note that while a conversion re-
source is enabled, all configuration selections related to it
may be changed except those outlined in Step 6.
–55–
A circuit for 2 V rms line-level inputs is shown in Figure 18.
Note that this is a divide-by-two resistive divider, and that the
line input is being used in a single-ended configuration. The
1 F ac-coupling capacitor may be of any type (tantalum is a
popular choice).
If line-level inputs are already at the 1 V rms levels expected by
the AD1843, the circuit shown in Figure 19 below should be
used. Note that when single-ended line inputs are desired, only
the LINRP and LINLP pins are used. DO NOT use the
LINRN or LINLN pins if the line input is single-ended.
The three auxiliary inputs, the SUM inputs, and the mono in-
put of the AD1843 present an input impedance which is lower
than the stereo line input. The circuit shown in Figure 20
should be used with 2 V rms swings on these inputs. With 1 V
rms swings, the circuit in Figure 19 above should be used.
For optimal performance, the AD1843 includes provision for a
differential configuration of the LIN inputs. Figure 21 illus-
trates a simple single-ended to differential converter. For the
best noise immunity, the circuitry to the left of the dotted line
should be located as close to the driving signal source as possible.
The 0.9K resistor and the 1000 pF capacitor are manda-
tory when using the LINRN and/or the LINLN inputs.
Furthermore, the 0.9K resistor and the 1000 pF NPO capacitor
should be located as close to the AD1843 as possible. If the
output range of the source does not match that of the AD1843
input, the op amp gain setting resistor values should be scaled
to match the source voltage range to the AD1843 input voltage
range.
Inexpensive feedback capacitors can be added (as shown in the
Figure 21 with dotted lines) for additional noise filtering (6 dB
per octave). Without the additional filter capacitor, there is a
single antialiasing pole at approximately 160 kHz. There is
Figure 20. AD1843 2 V rms Aux, SUM, and Mono Input
Circuits
Figure 19. AD1843 1 V rms Single-Ended Line-Level
Input Circuit
Figure 18. AD1843 2 V rms Single-Ended Line-Level
Input Circuit
3.3k
1nF
4.1k
1µF
5.1k
5.1k
3.3k
AUX1L
AUX2L
AUX3L
SUML
1nF
1nF
1nF
1µF
1µF
4.1k
1µF
5.1k
5.1k
1µF
1µF
3.3k
1nF
MIN
LINRP
LINLP
LINRP
LINLP
AD1843
4.1k
1µF
AUX1R
AUX2R
AUX3R
SUMR