AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 7

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

PIN DESCRIPTION
Serial Interface
Pin Name
SCLK
SDFS
SDI
SDO
BM
REV. 0
PQFP
79
2
80
1
10
AUX3R
AUX2R
AUX1R
AUX3L
AUX2L
AUX1L
GNDD
GNDD
SDFS
MICR
MICL
SDO
TSO
V
V
V
MIN
TSI
BM
CS
DD
DD
CC
TQFP
99
2
100
1
12
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
80
21
79
22
I/O
I/O
I/O
I
O
I
78
23
77
24
76
25
Description
Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output
to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock
as an input when the BM pin is driven LO. When the AD1843 is configured in
master mode, the SCLK frequency may be set to either 12.288 MHz or 16.384 MHz
with the SCF bit in Control Register Address 26.
Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame
synchronization signal as an output to the serial bus when the Bus Master (BM)
pin is driven HI and accepts the frame synchronization signal as an input when
the BM pin is driven LO.
Serial Data Input. SDI is used by peripheral devices such as the host CPU or a
DSP to supply control and playback data information to the AD1843. All control
and playback transfers are 16 bits long, MSB first.
Serial Data Output. SDO is used to supply status/control register readback and
capture data information to peripheral devices such as the host CPU or a DSP.
All status/control register readback and capture data transfers are 16 bits long,
MSB first. A three-state output driver is used on this pin.
Bus Master. When BM is tied HI the AD1843 is the serial bus master. The
AD1843 will then supply the serial clock (SCLK) and the frame sync (SDFS)
signals for the serial bus. No more than one device (AD1843/CPU/DSP) should
be configured as the serial bus master. When BM is tied LO, the AD1843 is con-
figured as a bus slave, and will accept the SCLK and SDFS signals as inputs. The
logic level on this pin must not be changed once RESET is deasserted (driven HI).
75
26
PIN CONFIGURATIONS
74
27
73
80-Lead PQFP
28
72
29
(Not to Scale)
AD1843
TOP VIEW
71
30
–7–
70
31
69
32
68
33
67
34
66
35
65
36
64
37
63
38
39
62
61
40
57
44
60
59
58
56
55
54
53
52
51
50
49
48
47
46
45
43
42
41
GNDD
XCTL1
XCTL0
SYNC3
SYNC2
SYNC1
RESET
PWRDWN
PDMNFT
HPOUTL
HPOUTC
HPOUTR
SUML
SUMR
GNDD
V
V
GNDA
V
V
DD
DD
CC
CC
AD1843