AD1845JP Analog Devices Inc, AD1845JP Datasheet - Page 23

• Manufacturer Part Number: AD1845JP
• Description: IC CODEC STEREO 5V 16BIT 68PLCC
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1845JP

• Rohs Status: RoHS non-compliant
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 81 / 82
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC

LB7:0
This register’s initial state after reset is “0000 0000.”
Expanded Modes (MODE2 = 1)
The following registers are enabled when the AD1845 is operating in MODE2 only.
DACZ
LMG4:0
TE
OL
This register’s initial state after reset is “0001 0001.”
res
RMG4:0
RMME
LMME
This register’s initial state after reset is “0001 000x.”
LLG4:0
res
REV. C
Lower Base Count Register (IXA3:0 = 15)
Alternate Feature Enable/Left MIC Input Control Register (IXA3:0 = 16)
MIC Mix Enable/Right MIC Input Control Register (IXA3:0 = 17)
Left Line Gain, Attenuate, Mute Mix Register (IXA3:0 = 18)
IXA3:0
IXA3:0
IXA3:0
IXA3:0
15
16
17
18
Left Line Mix Gain. Allows setting the left line mix gain in thirty-two 1.5 dB steps. See Figure 10 for mix gain
level setting.
Reserved for future expansion. Always write zeros to these bits.
Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits
of the 16-bit base register. Reads from this register return the same value which was written. The current count
contained in the counters cannot be read.
DAC Zero. When an underrun error occurs, this bit will force the DAC output to midscale.
0
1
Left MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. LMG4:0 = 0 produces
a +12 dB gain. LMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
Timer Enable. Setting this bit enables the 16-bit programmable timer (see Registers 20 and 21). When the timer
is enabled, the timer count is reloaded, and interrupts are generated at specified periods on the INT pin. When the
timer is disabled, the timer stops counting and the INT pin and TI bit are cleared immediately.
Output Level. This bit sets the analog output level. The line output level may be attenuated by 3 dB.
0
1
Reserved for future expansion. Always write zero to this bit.
Right MIC Gain. The least significant bit of this gain/attenuate select represents 1.5 dB. RMG4:0 = 0 produces a
+12 dB gain. RMG4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 dB.
See Figure 10.
Right MIC Mix Enable. Setting this bit enables the right microphone input to be mixed with the DAC output on
R_OUT.
Left MIC Mix Enable. Setting this bit enables the left microphone input to be mixed with the DAC output on
L_OUT.
LMME
Data 7
Data 7
Data 7
Data 7
LLM
LB7
Output previous valid sample
Output to midscale value
Full scale of 2.0 V p-p (–3 dB)
Full scale of 2.8 V p-p (0 dB)
OL
RMME
Data 6
Data 6
Data 6
Data 6
LB6
TE
res
Data 5
Data 5
LMG4
Data 5
RMG4
Data 5
LB5
res
–23–
Data 4
Data 4
Data 4
RMG3
LMG3
Data 4
LLG4
LB4
Data 3
Data 3
Data 3
RMG2
LMG2
Data 3
LLG3
LB3
Data 2
Data 2
Data 2
RMG1
LMG1
Data 2
LLG2
LB2
Data 1
Data 1
Data 1
RMG0
LMG0
Data 1
LLG1
LB1
Data 0
Data 0
DACZ
Data 0
AD1845
Data 0
LLG0
LB0
res