AD1845JP-REEL Analog Devices Inc, AD1845JP-REEL Datasheet - Page 21

• Manufacturer Part Number: AD1845JP-REEL
• Description: IC CODEC STEREO 5V 16BIT 68PLCC
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1845JP-REEL

• Rohs Status: RoHS non-compliant
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 81 / 82
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC

XCTL1:0
This register’s initial state after reset is “00xx xx00.”
ORL1:0
ORR1:0
DRS
ACI
PUR
COR
The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit
is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while check-
ing other status bits.
This register’s initial state after reset is “0000 0000.”
ID3:0
BUF8
res
REV. C
Test and Initialization Register (IXA3:0 = 11)
Miscellaneous Control Register (IXA3:0 = 12)
IXA3:0
IXA3:0
11
12
External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845.
Overrange Left Detect. These bits indicate the overrange on the left capture channel. These bits change on
Overrange Right Detect. These bits indicate the overrange on the right capture channel. These bits change
AD1845 Revision ID. These four bits define the revision level of the AD1845. The AD1845 will have ID =
0
1
a sample-by-sample basis, and are read-only.
ORL1
0
0
1
1
on a sample-by-sample basis, and are read-only.
ORR1
0
0
1
1
Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1845.
0
1
Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change
Enable (MCE). This bit is read-only.
0
1
Playback Underrun. This bit is set when the playback FIFO is empty and after the next valid sample has been
played back. If this condition exists, DACZ determines the DAC playback value. In MODE1, DACZ is always set
and returns a midscale value.
Capture Overrun. This bit is set when the capture FIFO is full and an additional sample has been captured. The
sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on
a sample by sample basis.
“1010.” These bits are read-only.
Parallel Interface Bus Transceiver Current Buffer Drive. The AD1845 can be programmed to provide a current
drive of 16 mA or 8 mA.
0
1
Reserved for future expansion. Always write 0s to these bits.
Data 7
Data 7
COR
MID
Logic LO on XCTL1:0 pins
Logic HI on XCTL1:0 pins
ORL0
0
1
0
1
ORR0
0
1
0
1
CDRQ and PDRQ are presently inactive (LO)
CDRQ or PDRQ are presently active (HI)
Autocalibration is not in progress
Autocalibration is in progress or MCE was exited within the last 128 sample periods
16 mA current drive.
8 mA current drive.
MODE2
Data 6
Data 6
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
PUR
Data 5
Data 5
ACI
res
–21–
Data 4
Data 4
BUF8
DRS
Data 3
Data 3
ORR1
ID3
Data 2
Data 2
ORR0
ID2
Data 1
Data 1
ORL1
ID1
Data 0
Data 0
AD1845
ORL0
ID0