ADV601JS12 Analog Devices Inc, ADV601JS12 Datasheet
ADV601JS12
Specifications of ADV601JS12
Related parts for ADV601JS12
ADV601JS12 Summary of contents
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FEATURES Precise Compressed Bit Rate Control Field Independent Compression Flexible Video Interface Supports All Common Formats, Including CCIR-656 General Purpose 8-, 16- or 32-Bit Host Interface With 512 Deep 32-Bit FIFO PERFORMANCE Real-Time Compression Or Decompression of CCIR-601 And ...
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ADV601 TABLE OF CONTENTS This data sheet gives an overview of the ADV601 functionality and provides details on designing the part into a system. The text of the data sheet is written for an audience with a general knowledge of ...
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The sub-band coding architecture of the ADV601 provides a number of options to stretch compression perfor- mance. These options are outlined on in the Applying the ADV601 section. The DSP serial port interface (SPORT) enables performance of Bin Width ...
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ADV601 THE WAVELET KERNEL This block contains a set of filters and decimators that work on the image in both horizontal and vertical directions. Figure 6 illustrates the filter tree structure. The filters apply carefully chosen wavelet basis functions that ...
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Figure 4. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) REV. 0 Figure 5. Modified Mallat Diagram of Image –5– ADV601 ...
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ADV601 LUMINANCE AND COLOR COMPONENTS (EACH SEPARATELY) HIGH LOW PASS IN PASS HIGH LOW PASS IN PASS IN BLOCK HIGH LOW HIGH PASS IN PASS IN ...
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THE PROGRAMMABLE QUANTIZER This block quantizes the filtered image based on the response profile of the human visual system. In general, the human eye cannot resolve high frequencies in images to the same level of accuracy as lower frequencies. Through ...
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ADV601 Table II. ADV601 Typical Quantization of Mallat Data Block 1 Data Mallat Bin Width Blocks Factors 39 0x007F 40 0x009A 41 0x009A 36 0x00BE 33 0x00BE 30 0x00E4 34 0x00E6 35 0x00E6 37 0x00E6 38 0x00E6 31 0x0114 32 ...
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REGISTER ADDRESS BYTE 3 RESERVED 0x0 RESERVED 0x4 0x8 RESERVED 0xC INDIRECT (INTERNALLY INDEXED) REGISTERS {ACCESS THESE REGISTERS THROUGH THE INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} Figure 9. Map of ADV601 Direct and Indirect Registers REV. 0 DIRECT ...
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ADV601 ADV601 REGISTER DESCRIPTIONS Indirect Address Register Direct (Write) Register Byte Offset 0x00. This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All indirect write registers are 16-bits ...
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FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV601’s compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until MERR ...
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ADV601 [5] Video Interface Master/Slave Mode Select, M/S. This bit selects the following: 0 Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value 1 Master mode video interface (ADV601 controls video timing, HSYNC-VSYNC are outputs) ...
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VIDEO AREA REGISTERS The area defined by the HSTART, HEND, VSTART and VEND registers is the active area that the wavelet kernel processes. Video data outside the active video area is set to minimum luminance and zero chrominance (black) by ...
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ADV601 Compression Ratio Register Indirect (Write Only) Register Index 0x06 This register holds the value that is used by the DSP to control compression during encode mode. Note that this register should only be used when a DSP is calculating ...
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MIN Luma Value Register Indirect (Read Only) Register Index 0x0AD The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed data. The Host reads these values through the ...
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ADV601 Clock Pins Name Pins I/O VCLK/XTAL 2 I VCLKO 1 O Video Interface Pins Name Pins I/O VSYNC HSYNC FIELD ENC 1 O VDATA[19:0] 20 I/O CREF ...
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DRAM Interface Pins Name Pins I/O DDAT[15:0] 16 I/O DADR[8: RAS 1 O CAS Serial Port Pins and Timing DSP Interface Pins Name Pins I/O TXD 1 O RXD 1 I TCLK 1 ...
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ADV601 DSP Interface Pins (Continued) Name Pins I DIRQ 1 O Host Interface Pins Name Pins I/O DATA[31:0] 32 I/O ADR[1: BE0–BE3 4 I Description Serial Transmit Frame Sync. Connect this pin ...
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Host Interface Pins (Continued) Name Pins I/O BE0–BE3 (Cont ACK 1 O FIFO_ERR 1 O FIFO_SRQ 1 O REV. 0 Description Some important notes for 8- and 16-bit interfaces ...
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ADV601 Host Interface Pins (Continued) Name Pins I/O FIFO_STP 1 O STATS_R 1 O LCODE 1 O HIRQ 1 O RESET 1 I Power Supply Pins Name Pins I/O GND 28 I VDD 21 I Description FIFO Stop. This condition ...
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Video Interface The ADV601 video interface supports a wide range of compo- nent digital video (D1) interfaces in both compression (input) and decompression (output) modes. These digital video inter- faces include support for the following: • Philips 4:2:2 • Multiplexed ...
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ADV601 • Active Area Control Four registers HSTART (horizontal start), HEND (horizon- tal end), VSTART (vertical start) and VEND (vertical end) determine the active video area. The maximum active video area is 768 by 288 pixels for a single field. ...
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Video Formats—CCIR-656 The ADV601 supports a glueless video interface to CCIR-656 devices when the Video Format is programmed to CCIR-656 mode. CCIR-656 requires that 4:2:2 data ( bits per com- ponent) be multiplexed and transmitted over a single ...
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ADV601 Video Formats — Multiplexed Philips Video The ADV601 supports a hybrid mode of operation that is a cross between standard dual lane Philips and single lane CCIR-656. In this mode, video data is multiplexed in the same fashion in ...
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Host Interface The ADV601 host interface is a high performance interface that passes all command and real-time compressed video data be- tween the host and codec. A 512 position by 32-bit wide, bidi- rectional FIFO buffer passes compressed video data ...
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ADV601 DRAM Manager The DRAM Manager provides a sorting and reordering func- tion on the sub-band coded data between the Wavelet Kernel and the Programmable Quantizer. The DRAM manager pro- vides a pipeline delay stage to the ADV601. This pipeline ...
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Table XIV. Pseudo-Code Describing a Sequence of Video Fields Complete Sequence: <Field 1 Sequence> <Field 2 Sequence> <Field 1 Sequence> <Field 2 Sequence> (Field Sequences) <Field 1 Sequence> <Field 2 Sequence> #EOS Field 1 Sequence: #SOF1 <VITC> <First Block Sequence> ...
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ADV601 In general, a Frame of data is made up of odd and even Fields as shown in Figure 12. Each Field Sequence is made First Block Sequence and a Complete Block Sequence. The First Block Sequence ...
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Table XV. Pseudo-Code of Compressed Video Data Bitstream for One Field of Video Block Sequence Data #SOFn<VITC><TYPE3><BW><Huff_Data> #SOB4<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> #SOB3<BW><Huff_Data> #SOB1<BW><Huff_Data> ...
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ADV601 Table XVII. ADV601 Field and Block Delimiters (Codes) Code Name Code #SOF1 0xffffffff40000000 #SOF2 0xffffffff41000000 <VITC> (96 bits) <TYPE1> 0x81 <TYPE2> 0x82 <TYPE3> 0x83 <TYPE4> 0x84 #SOB1 0xffffffff81 #SOB2 0xffffffff82 #SOB3 0xffffffff83 #SOB4 0xffffffff84 #SOB5 0xffffffff8f Description (Align all ...
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Table XVIII. ADV601 Field and Block Delimiters (Codes) Code Name Code <BW> (16 bits, 8.8) <HUFF_DATA> (Modulo 32) #EOS 0xffffffffc0ffffff Table XIX. Video Data Bitstream for One Field In a Video Sequence ffff ffff 4000 0000 0000 8400 00ff df0c ...
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ADV601 APPLYING THE ADV601 This section includes the following topics: • Using the ADV601 in computer applications • Using the ADV601 in standalone applications • Configuring the host interface for 8-, 16- or 32-bit data paths • Connecting the video ...
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A2 A3 D0–D7 SYSTEM DEPENDENT ASIC BE0 BE1 BE2 BE3 TFS RTF TD ADSP-21xx RD SCLK IRQ2 Figure 15. Suggested Standalone Application Design ADR1 ADR2 DATA0–7 DATA8-15 ADR0 ADSP-21csp01 CLKIN IOMS RD WR FLIN2 FLIN0 IRQ0 FLIN1 ...
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ADV601 The Bt819A has a horizontal scaling function that is used to implement the decimation from the 8xFsc rate to the required number of pixels per scan line (Pdesired). The value that must be programmed is HSCALE. • HSCALE = ...
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GETTING THE MOST OUT OF ADV601 The unique sub-band block structure of luminance and color components in the ADV601 offers many unique application benefits. Analog Devices will offer a Feature Software Library as well as separate feature application documentation to ...
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ADV601–SPECIFICATIONS The ADV601 video codec uses a Bi-Orthogonal (7, 9) Wavelet Transform. RECOMMENDED OPERATING CONDITIONS Parameter Description V Supply Voltage DD T Ambient Operating Temperature AMB ELECTRICAL CHARACTERISTICS Parameter Description V Hi-Level Input Voltage IH V Lo-Level Input Voltage IL ...
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TEST CONDITIONS Figure 23 shows test condition voltage reference and device loading information. These test conditions consider an output as disabled when the output stops driving and goes from the measured high or low voltage to a high impedance state. ...
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ADV601 (I) VCLK (O) VCLKO (VCLK2 = 0) (I) VCLKO (VCLK2 = 1) NOTE: USE VCLK FOR CLOCKING VIDEO-ENCODE OPERATIONS AND USE VCLKO FOR CLOCKING VIDEO-DECODE OPERATIONS. DO NOT TRY TO USE EITHER CLOCK FOR BOTH ENCODE AND DECODE. CCIR-656 ...
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Figure 27. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLK0. REV. 0 –39– ADV601 ...
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ADV601 Gray Scale/Philips Video Timing The diagrams in this section show transfer timing for pixel (YCrCb), line (horizontal) and frame (vertical) data in Gray Scale or Philips video modes. All output values assume a maximum pin loading of 50 pF. ...
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Table XXVII. Gray Scale/Philips Encode and Master Video Timing Parameters Parameter Description t VDATA Bus, Encode Master Gray Scale/Philips, Setup VDATA_EMGP_S t VDATA Bus, Encode Master Gray Scale/Philips, Hold VDATA_EMGP_H t CTRL Signals, Encode Master Gray Scale/Philips, Delay CTRL_EMGP_D t ...
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ADV601 Figure 32. Gray Scale/Philips Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note: For CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLK0. –42– REV. 0 ...
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Multiplexed Philips Video Timing The diagrams in this section show transfer timing for pixel (YCrCb) data in Multiplexed Philips video mode. For line (horizontal) and frame (vertical) data transfer timing, see the Gray Scale/Philips Video Timing section. All output values ...
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ADV601 Table XXXI. Multiplexed Philips Video —Encode and Master Pixel (YCrCb) Timing Parameters Parameter Description t VDATA Bus, Encode Master Multiplexed Philips, Setup VDATA_EMM_S t VDATA Bus, Encode Master Multiplexed Philips, Hold VDATA_EMM_H t CTRL Signals, Encode Master Multiplexed Philips, ...
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Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV601’s direct registers, except the Compressed Data register. Accesses to ...
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ADV601 Table XXXIV. Host (Indirect Address, Indirect Data, and Interrupt Mask/Status) Write Timing Parameters Parameter Description WR Signal, Direct Register, Write Cycle Time (at 27 MHz VCLK) t WR_D_WRC WR Signal, Direct Register, Pulse Width Asserted (at 27 MHz VCLK) ...
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Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac- cesses to the Compressed Data register are faster than access timing for the ...
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ADV601 Table XXXVI. Host (Compressed Data) Write Timing Parameters Parameter Description WR Signal, Compressed Data Direct Register, Write Cycle time t WR_CD_WRC WR Signal, Compressed Data Direct Register, Pulse Width Asserted t WR_CD_PWA WR Signal, Compressed Data Direct Register, Pulse ...
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DSP Interface Timing The diagram in this section shows transfer timing for one set of video statistics and calculated bin widths as they pass through the ADV601’s DSP interface. Whenever an ADV601’s serial port is inactive, the codec’s TXD pin ...
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ADV601 Pin Pin Pin Name Type 1 DATA4 I/O 2 DATA3 I/O 3 DATA2 I/O 4 DATA1 I/O 5 DATA0 I/O 6 VDD POWER 7 GND GROUND ADR1 I 12 ...
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DATA4 1 PIN 1 DATA3 2 IDENTIFIER 3 DATA2 DATA1 4 5 DATA0 VDD 6 GND ADR1 11 ADR0 12 GND 13 BE3 14 BE2 15 BE1 16 BE0 17 GND 18 ...
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ADV601 0.041 (1.03) 0.035 (0.88) TYP 0.029 (0.73) SEATING PLANE 0.004 (0.10) 0.010 (0.25) Part Number Ambient Temperature Range ADV601JS +70 C NOTES Commercial temperature range ( +70 C ...