IC CODEC AUDIO 5V 16BIT 100-TQFP

AD1845JSTZ

Manufacturer Part NumberAD1845JSTZ
DescriptionIC CODEC AUDIO 5V 16BIT 100-TQFP
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JSTZ datasheet
 


Specifications of AD1845JSTZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case100-TQFP, 100-VQFPLead Free Status / RoHS StatusLead free / RoHS Compliant
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FEATURES
Single-Chip Integrated
Digital Audio Stereo Codec
®
®
Microsoft
and Windows
Sound System Compatible
MPC Level-2+ Compliant Mixing
16 mA Bus Drive Capability
Supports Two DMA Channels for Full Duplex Operation
On-Chip Capture and Playback FIFOs
Advanced Power-Down Modes
Programmable Gain and Attenuation
Sample Rates from 4.0 kHz to 50 kHz Derived from a
Single Clock or Crystal Input
68-Lead PLCC, 100-Lead TQFP Packages
Operation from +5 V Supplies
Byte-Wide Parallel Interface to ISA and EISA Buses
Pin Compatible with AD1848, AD1846, CS4248, CS4231
PRODUCT OVERVIEW
The Parallel Port AD1845 SoundPort Stereo Codec integrates
key audio data conversion and control functions into a single
integrated circuit. The AD1845 provides a complete, single chip
computer audio solution for business audio and multimedia
applications. The codec includes stereo audio converters, com-
ANALOG
ANALOG SUPPLY
L_MIC
0 dB/
20 dB
R_MIC
L_LINE
R_LINE
L_AUX1
R_AUX1
GAM
L_OUT
M_OUT
MUTE
R_OUT
M_IN
L_AUX2
R_AUX2
SoundPort is a registered trademark of Analog Devices, Inc.
Microsoft and Windows are registered trademarks of Microsoft Corporation.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
plete on-chip filtering, MPC Level-2 compliant analog mixing,
programmable gain, attenuation and mute, a variable sample
frequency generator, FIFOs, and supports advanced power-
down modes. It provides a direct, byte-wide interface to both
ISA (“AT”) and EISA computer buses for simplified implemen-
tation on a computer motherboard or add-in card.
The AD1845 SoundPort Stereo Codec supports a DMA re-
quest/grant architecture for transferring data with the host com-
puter bus. One or two DMA channels can be supported.
Programmed I/O (PIO) mode is also supported for control
register accesses and for applications lacking DMA control.
Two input control lines support mixed direct and indirect ad-
dressing of thirty-seven internal control registers over this asyn-
chronous interface. The AD1845 includes dual DMA count
registers for full duplex operation enabling the AD1845 to cap-
ture data on one DMA channel and play back data on a separate
channel. The FIFOs on the AD1845 reduce the risk of losing
data when making DMA transfers over the ISA/EISA bus. The
FIFOs buffer data transfers and allow for relaxed timing in
acknowledging requests for capture and playback data.
FUNCTIONAL BLOCK DIAGRAM
DIGITAL SUPPLY
CLOCK SOURCE
VARIABLE SAMPLE
FREQUENCY GENERATOR
L
A/D
M
GAIN
CONVERTER
U
X
R
A/D
GAIN
CONVERTER
GAM = GAIN
GAM
GAM
ATTENTUATE
MUTE
L
D/A
ATTENUATE
CONVERTER
MUTE
R
D/A
ATTENUATE
MUTE
CONVERTER
GAM
GAM
REFERENCE
V
V
REF_F
REF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
Tel: 781/329-4700
Fax: 781/326-8703
Parallel-Port 16-Bit
®
SoundPort
Stereo Codec
AD1845
(Continued on Page 9)
POWER DOWN
RESET
DIGITAL
AD1845
PLAYBACK REQ
PLAYBACK ACK
-LAW
CAPTURE REQ
A-LAW
FIFO
LINEAR
CAPTURE ACK
P
A
ADR1:0
R
A
DATA7:0
L
DIGITAL MIX
L
CS
ATTENUATE
E
L
RD
P
WR
O
-LAW
R
A-LAW
FIFO
BUS DRIVER
T
CONTROL
LINEAR
HOST DMA
INTERRUPT
EXTERNAL
CONTROL
CONTROL
REGISTERS
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997

AD1845JSTZ Summary of contents

  • Page 1

    FEATURES Single-Chip Integrated Digital Audio Stereo Codec ® ® Microsoft and Windows Sound System Compatible MPC Level-2+ Compliant Mixing 16 mA Bus Drive Capability Supports Two DMA Channels for Full Duplex Operation On-Chip Capture and Playback FIFOs Advanced Power-Down ...

  • Page 2

    AD1845–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1008 Analog Output Passband kHz ADC FFT ...

  • Page 3

    ANALOG-TO-DIGITAL CONVERTERS Resolution Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) THD+N (Referenced to Full Scale) Signal-to-Intermodulation Distortion ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to MIC ...

  • Page 4

    AD1845 SYSTEM SPECIFICATIONS System Frequency Response Ripple (Line In to Line Out)* Differential Nonlinearity* Phase Linearity Deviation* STATIC DIGITAL SPECIFICATIONS High Level Input Voltage ( Digital Inputs XTAL1I Low Level Input Voltage ( High Level Output ...

  • Page 5

    POWER SUPPLY Power Supply Range–Digital and Analog Power Supply Current Analog Supply Current Digital Supply Current Power Dissipation (Current Nominal Supplies) Power-Down Supply Current Reset Supply Current Total Power-Down Supply Current Standby Supply Current Mixer Power-Down Supply Current Mixer Only ...

  • Page 6

    AD1845 ADR0 CDAK CDRQ PDAK PDRQ V 68-Lead PLCC DD GNDD XTAL1I XTAL1O V DD GNDD XTAL2I XTAL2O PWRDWN RESET GNDD R_FILT ADR0 CDAK 6 CDRQ 7 PDAK 8 PDRQ 9 ...

  • Page 7

    Parallel Interface Pin Name PLCC TQFP I/O CDRQ CDAK PDRQ PDAK ADR1:0 9 & 10 100 & ...

  • Page 8

    AD1845 Analog Signals Pin Name PLCC TQFP I/O L_LINE R_LINE L_MIC R_MIC L_AUX1 R_AUX1 L_AUX2 R_AUX2 ...

  • Page 9

    Power Supplies Pin Name PLCC TQFP V 35 & & GNDA 34 & & 15, 10, 14, DD 19, 45, 55, 68, 54 88, 98 GNDD 2, 8, 16, 11, ...

  • Page 10

    AD1845 FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1845 and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. ...

  • Page 11

    COMPRESSED MSB LSB INPUT DATA 15 EXPANSION MSB 15 MSB DAC INPUT Figure 2. -Law or A-Law Expansion When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified. 15 MSB ADC OUTPUT ...

  • Page 12

    AD1845 A write read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are ...

  • Page 13

    Direct Registers ADRl:0 Data 7 0 INIT 1 IXD7 2 CU/L 3 CD7 3 PD7 Indirect Registers IXA3:0 Data 7 0 LSS1 1 RSS1 2 LMX1 3 RMX1 4 LMX2 5 RMX2 6 LDM 7 RDM 8 FMT1 9 CPIO ...

  • Page 14

    AD1845 DIRECT CONTROL REGISTER DEFINITIONS Index Address Register (ADR1 ADR1:0 Data 7 0 INIT IXA4:0 Index Address. These bits define the address of the AD1845 register accessed by the Indexed Data Register. These bits are read/write. IXA4 is ...

  • Page 15

    Status Register (ADR1 ADR1:0 Data 7 Data 6 2 CU/L INT Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1845. This bit is cleared by any host write of ...

  • Page 16

    AD1845 PIO Data Registers (ADR1 ADR1:0 Data 7 Data 6 3 CD7 3 PD7 The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will ...

  • Page 17

    RSS1 RSS0 Right Input Source 0 0 Right Line Source Selected 0 1 Right Auxiliary 1 Source Selected 1 0 Right Microphone Source Selected 1 1 Right Post-Mixed DAC Output Source Selected This register’s initial state after reset is “000x ...

  • Page 18

    AD1845 RX2A4:0 Right Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents 1.5 dB. RX2A4 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 ...

  • Page 19

    Clock and Data Format Register (IXA3 IXA3:0 Data 7 8 FMT1 FMT0 NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the sample rate. However, changes to FMT[1:0], C/L, and S/M ...

  • Page 20

    AD1845 Interface Configuration Register (IXA3 IXA3:0 Data 7 Data 6 9 CPIO NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the CEN and PEN bits in this register. PEN Playback ...

  • Page 21

    XCTL1:0 External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845. 0 Logic LO on XCTL1:0 pins 1 Logic HI on XCTL1:0 pins This register’s initial state after reset is “00xx xx00.” Test and ...

  • Page 22

    AD1845 MODE2 When the AD1845 is initialized, the MODE2 bit is set to 0, LO, and the AD1845 is register set compatible with the AD1848 and the AD1846. Setting the MODE2 bit to 1, HI, enables access to the indirect ...

  • Page 23

    Lower Base Count Register (IXA3:0 = 15) IXA3:0 Data 7 Data 6 15 LB7 LB7:0 Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. ...

  • Page 24

    AD1845 LLM Left Line Mute. Setting this bit to 1 mutes the left line input into the output mixer. This register’s initial state after reset is “1xx0 1000.” Right Line Gain, Attenuate, Mute, Mix Register (IXA3:0 = 19) IXA3:0 Data ...

  • Page 25

    Upper Timer Bits Register (IXA3:0 = 21) IXA3:0 Data 7 Data 6 21 TU7 TU7:0 Upper Timer Bits. This byte is the upper byte of the timer register containing the eight most significant bits of the 16-bit register. Reads from ...

  • Page 26

    AD1845 TI Timer Interrupt. This bit indicates that there is an interrupt pending from the timer count registers. res Reserved for future expansion. Always write zero to this bit. Playback, Capture and timer interrupts may be cleared simultaneously by writing ...

  • Page 27

    Power-Down Control Register (IXA3:0 = 27) IXA3:0 Data 7 27 ADCPWD DACPWD res Reserved for future expansion. Always write zeros to these bits. FREN Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers ...

  • Page 28

    AD1845 XFS2:0 Crystal/Clock Input Frequency Select. On power up or reset, the AD1845 expects a 24.576 MHz input clock. If the clock source connected to the AD1845 is different from the default condition, then the clock input must be selected ...

  • Page 29

    DATA AND CONTROL TRANSFERS The AD1845 SoundPort Stereo Codec supports a DMA re- quest/grant architecture for transferring data with the host com- puter bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for ...

  • Page 30

    AD1845 is activated when both Playback Enable (PEN) is set and Play- back PIO (PPIO) is set. Capture PIO is activated when both Capture Enable (CEN) is set and Capture PIO (CPIO) is set. See Figures 20 and 21 for ...

  • Page 31

    Switching between playback and capture in Single-Channel DMA mode does not require changing the PPIO and CPIO bits or passing through the Mode Change Enable state except for initial setup. For setup, assign zeros to both PPIO and CPIO. This ...

  • Page 32

    AD1845 POWER-UP AND RESET The PWRDWN and RESET pin should be held in the active LO state when power is first applied to the AD1845. The AD1845’s initialization commences when PWRDWN and RESET have both been deasserted (HI). While initializing, ...

  • Page 33

    The AD1845 performs a sequenced power-down that eliminates audible effects from the DAC’s output, and saves the codec’s internal operating state. Clearing the bits (writing a “0” to the control bits) returns the AD1845 from the power-down state and begins ...

  • Page 34

    AD1845 In the Expanded Mode, MODE2, the AD1845 can be pro- grammed to change the sample rate selection incre- ments “on the fly” and without entering the Mode Change Enable Sequence. The following sequence applies to the ...

  • Page 35

    Figure 30 shows ac-coupled line outputs. The resistors are used to center the output signals around analog ground. If dc-cou- pling is desired, V could be used with op amps as mentioned REF above, if desired L_OUT 47k ...

  • Page 36

    AD1845 Analog Devices recommends that all digital pins be driven from the same supply. A common technique to achieve maximum performance is to use regulator to power the analog side of the codec from the PCs +12 ...

  • Page 37

    FREQUENCY RESPONSE PLOTS 10 0 –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SAMPLE FREQUENCY – F Figure 37. Analog-to-Digital Frequency Response to F (Full-Scale Line-Level Inputs, 0 ...

  • Page 38

    AD1845 EXTENDED TEMPERATURE SPECIFICATIONS Test Conditions The AD1845 has been tested over the industrial temperature range. The typical values represent the limits that change with tempera- ture. All other limits remain unchanged. Temperature – +85 C Digital Supply ...

  • Page 39

    TABLE OF CONTENTS PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Expanded Mode (MODE2) . ...

  • Page 40

    AD1845 0.030 (0.75) 0.020 (0.50) MAX LEAD COPLANARITY OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (P-68A) 0.175 (4.45) 0.995 (25.27) 0.169 (4.29) SQ 0.885 (22.48 PIN 1 0.050 ...