AD1845JSTZ Analog Devices Inc, AD1845JSTZ Datasheet
AD1845JSTZ
Specifications of AD1845JSTZ
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AD1845JSTZ Summary of contents
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FEATURES Single-Chip Integrated Digital Audio Stereo Codec ® ® Microsoft and Windows Sound System Compatible MPC Level-2+ Compliant Mixing 16 mA Bus Drive Capability Supports Two DMA Channels for Full Duplex Operation On-Chip Capture and Playback FIFOs Advanced Power-Down ...
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AD1845–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1008 Analog Output Passband kHz ADC FFT ...
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ANALOG-TO-DIGITAL CONVERTERS Resolution Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) THD+N (Referenced to Full Scale) Signal-to-Intermodulation Distortion ADC Crosstalk* Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line to MIC ...
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AD1845 SYSTEM SPECIFICATIONS System Frequency Response Ripple (Line In to Line Out)* Differential Nonlinearity* Phase Linearity Deviation* STATIC DIGITAL SPECIFICATIONS High Level Input Voltage ( Digital Inputs XTAL1I Low Level Input Voltage ( High Level Output ...
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POWER SUPPLY Power Supply Range–Digital and Analog Power Supply Current Analog Supply Current Digital Supply Current Power Dissipation (Current Nominal Supplies) Power-Down Supply Current Reset Supply Current Total Power-Down Supply Current Standby Supply Current Mixer Power-Down Supply Current Mixer Only ...
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AD1845 ADR0 CDAK CDRQ PDAK PDRQ V 68-Lead PLCC DD GNDD XTAL1I XTAL1O V DD GNDD XTAL2I XTAL2O PWRDWN RESET GNDD R_FILT ADR0 CDAK 6 CDRQ 7 PDAK 8 PDRQ 9 ...
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Parallel Interface Pin Name PLCC TQFP I/O CDRQ CDAK PDRQ PDAK ADR1:0 9 & 10 100 & ...
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AD1845 Analog Signals Pin Name PLCC TQFP I/O L_LINE R_LINE L_MIC R_MIC L_AUX1 R_AUX1 L_AUX2 R_AUX2 ...
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Power Supplies Pin Name PLCC TQFP V 35 & & GNDA 34 & & 15, 10, 14, DD 19, 45, 55, 68, 54 88, 98 GNDD 2, 8, 16, 11, ...
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AD1845 FUNCTIONAL DESCRIPTION This section overviews the functionality of the AD1845 and is intended as a general introduction to the capabilities of the device. As much as possible, detailed reference information has been placed in “Control Registers” and other sections. ...
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COMPRESSED MSB LSB INPUT DATA 15 EXPANSION MSB 15 MSB DAC INPUT Figure 2. -Law or A-Law Expansion When 8-bit companding is specified, the ADCs’ linear output is compressed to the format specified. 15 MSB ADC OUTPUT ...
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AD1845 A write read from the Indexed Data Register will access the Indirect Register which is indexed by the value most recently written to the Index Address Register. The Status Register and the PIO Data Register are ...
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Direct Registers ADRl:0 Data 7 0 INIT 1 IXD7 2 CU/L 3 CD7 3 PD7 Indirect Registers IXA3:0 Data 7 0 LSS1 1 RSS1 2 LMX1 3 RMX1 4 LMX2 5 RMX2 6 LDM 7 RDM 8 FMT1 9 CPIO ...
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AD1845 DIRECT CONTROL REGISTER DEFINITIONS Index Address Register (ADR1 ADR1:0 Data 7 0 INIT IXA4:0 Index Address. These bits define the address of the AD1845 register accessed by the Indexed Data Register. These bits are read/write. IXA4 is ...
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Status Register (ADR1 ADR1:0 Data 7 Data 6 2 CU/L INT Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1845. This bit is cleared by any host write of ...
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AD1845 PIO Data Registers (ADR1 ADR1:0 Data 7 Data 6 3 CD7 3 PD7 The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0). Reads will ...
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RSS1 RSS0 Right Input Source 0 0 Right Line Source Selected 0 1 Right Auxiliary 1 Source Selected 1 0 Right Microphone Source Selected 1 1 Right Post-Mixed DAC Output Source Selected This register’s initial state after reset is “000x ...
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AD1845 RX2A4:0 Right Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents 1.5 dB. RX2A4 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is –34.5 ...
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Clock and Data Format Register (IXA3 IXA3:0 Data 7 8 FMT1 FMT0 NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the sample rate. However, changes to FMT[1:0], C/L, and S/M ...
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AD1845 Interface Configuration Register (IXA3 IXA3:0 Data 7 Data 6 9 CPIO NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the CEN and PEN bits in this register. PEN Playback ...
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XCTL1:0 External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845. 0 Logic LO on XCTL1:0 pins 1 Logic HI on XCTL1:0 pins This register’s initial state after reset is “00xx xx00.” Test and ...
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AD1845 MODE2 When the AD1845 is initialized, the MODE2 bit is set to 0, LO, and the AD1845 is register set compatible with the AD1848 and the AD1846. Setting the MODE2 bit to 1, HI, enables access to the indirect ...
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Lower Base Count Register (IXA3:0 = 15) IXA3:0 Data 7 Data 6 15 LB7 LB7:0 Lower Base Count. This byte is the lower byte of the base count register containing the eight least significant bits of the 16-bit base register. ...
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AD1845 LLM Left Line Mute. Setting this bit to 1 mutes the left line input into the output mixer. This register’s initial state after reset is “1xx0 1000.” Right Line Gain, Attenuate, Mute, Mix Register (IXA3:0 = 19) IXA3:0 Data ...
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Upper Timer Bits Register (IXA3:0 = 21) IXA3:0 Data 7 Data 6 21 TU7 TU7:0 Upper Timer Bits. This byte is the upper byte of the timer register containing the eight most significant bits of the 16-bit register. Reads from ...
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AD1845 TI Timer Interrupt. This bit indicates that there is an interrupt pending from the timer count registers. res Reserved for future expansion. Always write zero to this bit. Playback, Capture and timer interrupts may be cleared simultaneously by writing ...
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Power-Down Control Register (IXA3:0 = 27) IXA3:0 Data 7 27 ADCPWD DACPWD res Reserved for future expansion. Always write zeros to these bits. FREN Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers ...
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AD1845 XFS2:0 Crystal/Clock Input Frequency Select. On power up or reset, the AD1845 expects a 24.576 MHz input clock. If the clock source connected to the AD1845 is different from the default condition, then the clock input must be selected ...
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DATA AND CONTROL TRANSFERS The AD1845 SoundPort Stereo Codec supports a DMA re- quest/grant architecture for transferring data with the host com- puter bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for ...
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AD1845 is activated when both Playback Enable (PEN) is set and Play- back PIO (PPIO) is set. Capture PIO is activated when both Capture Enable (CEN) is set and Capture PIO (CPIO) is set. See Figures 20 and 21 for ...
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Switching between playback and capture in Single-Channel DMA mode does not require changing the PPIO and CPIO bits or passing through the Mode Change Enable state except for initial setup. For setup, assign zeros to both PPIO and CPIO. This ...
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AD1845 POWER-UP AND RESET The PWRDWN and RESET pin should be held in the active LO state when power is first applied to the AD1845. The AD1845’s initialization commences when PWRDWN and RESET have both been deasserted (HI). While initializing, ...
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The AD1845 performs a sequenced power-down that eliminates audible effects from the DAC’s output, and saves the codec’s internal operating state. Clearing the bits (writing a “0” to the control bits) returns the AD1845 from the power-down state and begins ...
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AD1845 In the Expanded Mode, MODE2, the AD1845 can be pro- grammed to change the sample rate selection incre- ments “on the fly” and without entering the Mode Change Enable Sequence. The following sequence applies to the ...
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Figure 30 shows ac-coupled line outputs. The resistors are used to center the output signals around analog ground. If dc-cou- pling is desired, V could be used with op amps as mentioned REF above, if desired L_OUT 47k ...
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AD1845 Analog Devices recommends that all digital pins be driven from the same supply. A common technique to achieve maximum performance is to use regulator to power the analog side of the codec from the PCs +12 ...
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FREQUENCY RESPONSE PLOTS 10 0 –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SAMPLE FREQUENCY – F Figure 37. Analog-to-Digital Frequency Response to F (Full-Scale Line-Level Inputs, 0 ...
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AD1845 EXTENDED TEMPERATURE SPECIFICATIONS Test Conditions The AD1845 has been tested over the industrial temperature range. The typical values represent the limits that change with tempera- ture. All other limits remain unchanged. Temperature – +85 C Digital Supply ...
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TABLE OF CONTENTS PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Expanded Mode (MODE2) . ...
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AD1845 0.030 (0.75) 0.020 (0.50) MAX LEAD COPLANARITY OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (P-68A) 0.175 (4.45) 0.995 (25.27) 0.169 (4.29) SQ 0.885 (22.48 PIN 1 0.050 ...