AD1849KPZ Analog Devices Inc, AD1849KPZ Datasheet - Page 10

• Manufacturer Part Number: AD1849KPZ
• Description: IC CODEC STEREO 5V 16BIT 44PLCC
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1849KPZ

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 83 / 86
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1849K
The loopback modes are shown graphically in Figure 3.
DISCONNECTED
FUNCTIONAL
FUNCTIONAL
LINE, MIC
LINE, MIC
OUTPUT
OUTPUT
LINE 0,
LINE 0,
LINE 1
LINE 1
INPUT
INPUT
MUTE
GAIN
GAIN
MUTE
AD1849K
0
1
AD1849K
A/D
D/A
A/D
D/A
MONITOR
MONITOR
DISABLE
ENCODE
ENCODE
ENCODE
DECODE
/A-LAW
/A-LAW
/A-LAW
/A-LAW
SDTX
SDRX
SDTX
SDRX
Clocks and Sample Rates
The AD1849K can operate from external crystals, from a 256 ×
F
factor, or from the serial port’s bit clock (at 256 × F
under software control. Two crystal inputs are provided to
generate a wide range of sample rates. The oscillators for these
crystals are on the AD1849K, as is a multiplexer for selecting
between them. They can be overdriven with external clocks by
the user, if so desired. The recommended crystal frequencies are
16.9344 MHz and 24.576 MHz. From them the following sample
rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025,
16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz.
Regardless of clock input source, a clock output of 256 × F
generated (with some skew). If an external input clock or the
serial port’s bit clocks are selected to drive the AD1849K’s
internal operation, they should be low jitter clocks. If no external
clock will be used, Analog Devices recommends tying the clock
input pin (CLKIN) to ground. If either external crystal is not
used, Analog Devices recommends tying its input (CIN1 and/or
CIN2) to ground.
S
input clock, from an input clock with a programmable divide
S
), selected
S
is