AD1849KPZ Analog Devices Inc, AD1849KPZ Datasheet - Page 18

• Manufacturer Part Number: AD1849KPZ
• Description: IC CODEC STEREO 5V 16BIT 44PLCC
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1849KPZ

• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 83 / 86
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1849K
TSIN is sampled on the falling edge of SCLK. A LO-to-HI
transition of TSIN defines the beginning of the word to occur at
the next rising edge of SCLK (for driving output data). The
LO-to-HI transition is defined by consecutive LO and HI
samples of TSIN at the falling edges of SCLK. Both input and
output data will be valid at the immediately subsequent falling
edge of SCLK. See Figures 6 and 7.
After the beginning of a word has been recognized, TSIN is a
“don’t care”; its state will be ignored until one SCLK period
before the end of the current word.
16-BIT STEREO DATA WORD
16-BIT MONO DATA WORD
CONTROL WORD
63
63
8-BIT STEREO DATA WORD
63
8-BIT MONO DATA WORD
63
63 61 60
FSYNC, TSIN, &
Left Audio 0000 0000 Right Audio 0000 0000
Left Audio
001 MB OLB DCB 0 AC
SDRX & SDTX
Left-Channel Audio
Left-Channel Audio
TSOUT
SCLK
56
56
59
55
55
0000 0000 Left Audio 0000 0000
58 57 56 55 54 53 51 50 49 48 47 46 44 43 42 41
48 47
48 47
48 47
Right-Channel Audio
Left-Channel Audio
00
40
DFR ST
39
FIRST DATA BIT
32 31
32 31 30 29 24 23
32 31 30 29 24 23 22 21
OF WORD
32 31 30 29 24 23 22 21
DF
OM
OM
OM
OM
ITS MCK FSEL MS TXDIS 0000 00 ENL ADL PIO 00 0000 0000 0000 0010 REVID 0000 0000
30 29 24 23 22 21
LO
LO
LO
LO
ADI SM
ADI SM
ADI SM
ADI SM
22 21
RO
RO
RO
RO
40
16 15 14
16 15 14
16 15 14
16 15 14
The AD1849K comes out of reset with the default conditions
specified in “Control Register Defaults.” It will be in the mode
specified by the D/C pin. If in Control Mode, the SoundPort
Codec can be configured by the host for operation. Subsequent
transitions to Control Mode after initialization are expected to
be relatively infrequent. Control information that is likely to
change frequently, e.g., gain levels, is transmitted along with the
data in Data Mode. See Figure 8 for a complete map of the data
and control information into the 64-bit Data Word and the
64-bit Control Word.
SDTX CONTROL
OR DATA BYTE 8,
BIT 0 OUTPUT
PIO INPUTS
PIO OUTPUTS
SCLK
SDRX AND TSIN
INPUTS
SDTX, FSYNC, AND
TSOUT OUTPUTS
SDTX CONTROL
OR DATA BYTE 1,
BIT 7 OUTPUT
39
PIO
PIO
PIO
PIO
34 33
OVR
OVR
OVR
OVR
13
13
13
13
12 11 8 7 4 3 0
IS
12 11 8 7 4 3 0
12 11 8 7 4 3 0
12 11 8 7 4 3 0
IS
IS
IS
32 31 30
LG
LG
LG
LG
MA
MA
MA
MA
29 24 23
t
t
ZV
D
t
HI
0000
0000
t
RG
RG
S
t
CLK
t
t
IH
D
16 15 12 11
t
t
t
OH
LO
VZ
t
S
t
IH
t
OH
8 7
0