AD1849KPZ Analog Devices Inc, AD1849KPZ Datasheet - Page 21

IC CODEC STEREO 5V 16BIT 44PLCC

AD1849KPZ

Manufacturer Part Number
AD1849KPZ
Description
IC CODEC STEREO 5V 16BIT 44PLCC
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of AD1849KPZ

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
83 / 86
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1849KPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
DCB = “0” until the echoed DCB from the Codec also is reset
to “0” (i.e., it must poll DCB until a “0” is read). This is the
first interlock of the DCB handshake.
The DCB = “0” is echoed on SDTX in the next frame after it
was received on SDRX if a sample rate has been consistently
selected AND the clock source is generated using the internal
oscillator. Otherwise DCB = “0” will be echoed on SDTX in
the frame after at least 2 ms of consistent sample rate selection
expires. If SCLK or CLKIN is used as the clock source, the user
must guarantee that the source selection and sample rate are stable
for 2 ms before D/C is driven HI.
Note that after sending a Control Word with DCB = “0,” the
external controller must take care not to set (or glitch) DCB =
“1” until after the echoed DCB = “0” has been received from
the Codec.
Second DCB Interlock
After it sees the DCB = “0” (and has optionally verified that
the echoed Control Word is correct), and when it is ready to
continue with the DCB handshake, the external controller
should transmit the desired and valid control information, but
now with DCB set to “1.” The external controller can then
transmit arbitrary control information until the echoed DCB
from the Codec is also set to “l” (i.e., it must poll DCB until a
“l” is read). After this Control Word with DCB = “1,” all future
control information received by the Codec during Control Mode
(i.e., while D/C is LO) will be ignored. This is the second and
final interlock of the DCB handshake.
The Codec will echo DCB = “l” in the next frame after it was
received on SDRX if a sample rate has been consistently selected
AND the clock source is generated using the internal oscillator.
Otherwise DCB = “1” will be echoed on SDTX once one sample
rate selection has been held constant for at least 2 ms. If SCLK
or CLKIN is used as the clock source, the user must guarantee
that the source selection and sample rate are stable for 2 ms
before D/C is driven HI. The Codec will transmit the full 64-bit
Control Word with DCB = “1” and then three-state the SDTX
pin. The external controller must continue to supply SCLK to
the Codec until all 64 bits of the Control Word with DCB = “1”
have been transmitted by the Codec, plus at least one [1] more
SCLK after this 64-bit Control Word (i.e., at least 65 SCLKs).
Note that echoing the full 64-bit Control Word makes the
AD1849K match the behavior of the CS4215.
Exit Control Mode
Control mode DCB handshake is now complete. The Codec
will remain inactive until D/C goes HI or RESET and or PDN
are asserted.
Note that if a sample rate and a clock source have been consist-
ently selected throughout the handshake, the AD1849K and the
CS4215 DCB protocols are equivalent.
Control Mode to Data Mode Transition and Autocalibration
The AD1849K will enter Data Mode when the asynchronous
D/C signal goes HI. The serial interface will become active
immediately and begin receiving and transmitting Data Words
in accordance with the SCLK, FSYNC, TSIN, and TSOUT
signals as shown in Figure 6. If the Codec enters Data Mode as
a master, it will generate one complete SCLK period before it
drives FSYNC HI; FSYNC will go HI with the second rising
edge of SCLK. This allows external devices driven by SCLK to
recognize a complete FSYNC LO-to-HI transition. If an
AD1849K Codec enters Data Mode as a slave, it can recognize
a TSIN LO-to-HI transition even if SCLK is simultaneously
making its first LO-to-HI transition. In fact, the AD1849K
serial interface will operate properly even if D/C, SCLK, and
TSIN all go HI at the same time.
See Figure 10 for a flow chart representation of a typical startup
sequence, including the DCB handshake.
APPLICATIONS CIRCUITS
The AD1849K Stereo Codec has been designed to require a
minimum of external circuitry. The recommended circuits are
shown in Figures 11 through 20 and summarized in Figure 21.
Analog Devices estimates that the total cost of all the compo-
nents shown in these Figures, including crystals, to be less than
$5 in 10,000 piece quantities.
Industry-standard compact disc “line-levels” are 2 V rms
centered around analog ground. (For other audio equipment,
“line level” is much more loosely defined.) The AD1849K
SoundPort is a 5 V only powered device. Line level voltage swings
for the AD1849K are defined to be 1 V rms for ADC input and
0.707 V rms for DAC output. Thus, 2 V rms input analog signals
must be attenuated and either centered around the reference
voltage intermediate between 0 V and 5 V or ac-coupled. The
CMOUT pin will be at this intermediate voltage, nominally
2.25 V. It has limited drive but can be used as a voltage datum to
an op amp input. Note, however, that dc-coupled inputs are not
recommended, as they provide no performance benefits with
the AD1849K architecture. Furthermore, dc offset differences
between multiple dc-coupled inputs create the potential for
“clicks” when changing the input mux selection.
Apply power while RESET is pulled LO
signals to Codec. Drive RESET
Transmit desired Control Word
HI (inactive) while D/C is LO
Wait for Codec to transmit
Wait for Codec to transmit
Transmit 194 Data Words
and wait 50 milliseconds
Transmit a Control Word
Provide TSIN and SCLK
to Codec with DCB LO
Begin audio operation
to Codec with DCB HI
back a DCB LO
back a DCB HI
Bring D/C HI
to Codec
ENTER CONTROL MODE
FIRST DCB INTERLOCK
EXIT CONTROL MODE
AUTOCALIBRATION
SECOND DCB INTERLOCK
0 – 2ms
AD1849K
0 – 2ms

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