AD1849KPZ Analog Devices Inc, AD1849KPZ Datasheet - Page 8

IC CODEC STEREO 5V 16BIT 44PLCC

AD1849KPZ

Manufacturer Part Number
AD1849KPZ
Description
IC CODEC STEREO 5V 16BIT 44PLCC
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of AD1849KPZ

Data Interface
Serial
Resolution (bits)
16 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
83 / 86
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD1849KPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD1849K
FUNCTIONAL DESCRIPTION
This section overviews the functionality of the AD1849K and
is intended as a general introduction to the capabilities of the
device. As much as possible, detailed reference information has
been placed in “Control Registers” and other sections. The user
is not expected to refer repeatedly to this section.
Analog Inputs
The AD1849K SoundPort Stereo Codec accepts stereo line-level
and mic-level inputs. These analog stereo signals are multiplexed
to the internal programmable gain amplifier (PGA) stage. The
mic inputs can be amplified by 20 dB prior to the PGA to com-
pensate for the voltage swing difference between line levels and
typical condenser microphones. The mic inputs can bypass the
20 dB fixed gain block and go straight to the input multiplexer,
which often results in an improved system signal-to-noise ratio.
The PGA following the input multiplexer allows independent
selectable gains for each channel from 0 to 22.5 dB in 1.5 dB
steps. The Codec can operate either in a global stereo mode or
in a global mono mode with left-channel inputs appearing at
both channel outputs.
Analog-to-Digital Datapath
The AD1849K Σ∆ ADCs incorporate a proprietary fourth-order
modulator. A single pole of passive filtering is all that is required
for antialiasing the analog input because of the ADC’s high 64
times oversampling ratio. The ADCs include linear-phase digital
decimation filters that low-pass filter the input to 0.45 × F
(“F
overrange conditions will cause a sticky bit to be set that can be
read.
Digital-to-Analog Datapath
The Σ∆ DACs are preceded by a programmable attenuator and
a low-pass digital interpolation filter. The attenuator allows
independent control of each DAC channel from 0 dB to –94.5 dB
in 1.5 dB steps plus full digital mute. The anti-imaging inter-
polation filter oversamples by 64 and digitally filters the higher
frequency images. The DACs’ Σ∆ noise shapers also oversample
by 64 and convert the signal to a single-bit stream. The DAC
outputs are then filtered in the analog domain by a combination
of switched-capacitor and continuous-time filters. They remove
the very high frequency components of the DAC bitstream
output, including both images at the oversampling rate and
shaped quantization noise. No external components are required.
Phase linearity at the analog output is achieved by internally
compensating for the group delay variation of the analog output
filters.
Attenuation settings are specified by control bits in the data
stream. Changes in DAC output level take effect only on zero
crossings of the digital signal, thereby eliminating “zipper”
noise. Each channel has its own independent zero-crossing
detector and attenuator change control circuitry. A timer
guarantees that requested volume changes will occur even in the
absence of an input signal that changes sign. The time-out
period is 10.7 milliseconds at a 48 kHz sampling rate and 64
milliseconds at an 8 kHz sampling rate (Time-out [ms] ≈ 512/
Sampling Rate [kHz]).
S
” is the word rate or “sampling frequency”). ADC input
S
Monitor Mix
A monitor mix is supported that digitally mixes a portion of the
digitized analog input with the analog output (prior to digitiza-
tion). The digital output from the ADCs going out of the serial
data port is unaffected by the monitor mix. Along the monitor
mix datapath, the 16-bit linear output from the ADCs is attenuated
by an amount specified with control bits. Both channels of
the monitor data are attenuated by the same amount. (Note
that internally the AD1849K always works with 16-bit PCM
linear data, digital mixing included; format conversions take
place at the input and output.)
Sixteen steps of –6 dB attenuation are supported to –94.5 dB. A
“0” implies no attenuation, while a “14” implies 84 dB of
attenuation. Specifying full scale “15” completely mutes the
monitor datapath, preventing any mixing of the analog input
with the digital input. Note that the level of the mixed output
signal is also a function of the input PGA settings since they
affect the ADCs’ output.
The attenuated monitor data is digitally summed with the DAC
input data prior to the DACs’ datapath attenuators. Because
both stereo signals are mixed before the output attenuators,
mix data is attenuated a second time by the DACs’ datapath
attenuators. The digital sum of digital mix data and DAC
input data is clipped at plus or minus full scale and does not
wrap around.
Analog Outputs
One stereo line-level output, one stereo headphone output, and
one monaural (mono) speaker output are available at external
pins. Each of these outputs can be independently muted. Muting
either the line-level stereo output or the headphone stereo
output mutes both left and right channels of that output. When
muted, the outputs will settle to a dc value near CMOUT,
the midscale reference voltage. The mono speaker output is
differential. The chip can operate either in a global stereo mode
or in a global mono mode with left channel inputs appearing at
both outputs.
Digital Data Types
The AD1849K supports four global data types: 16-bit twos-
complement linear PCM, 8-bit unsigned linear PCM, 8-bit
companded µ-law, and 8-bit companded A-law, as specified by
control register bits. Data in all four formats is always trans-
ferred MSB first. Sixteen-bit linear data output from the ADCs
and input to the DACs is in twos-complement format. Eight-bit
data is always left-justified in 16-bit fields; in other words, the
MSBs of all data types are always aligned; in yet other words,
full-scale representations in all three formats correspond to
equivalent full-scale signals. The eight least-significant bit positions
of 8-bit linear and companded data in 16-bit fields are ignored
on input and zeroed on output.
The 16-bit PCM data format is capable of representing 96 dB of
dynamic range. Eight-bit PCM can represent 48 dB of dynamic
range. Companded µ-law and A-law data formats use nonlinear
coding with less precision for large-amplitude signals. The loss
of precision is compensated for by an increase in dynamic range
to 64 dB and 72 dB, respectively.

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