IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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AD1845
PIO Data Registers (ADR1:0 = 3)
ADR1:0
Data 7
Data 6
3
CD7
3
PD7
The PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register
(PD7:0). Reads will receive data from the PIO Capture Data Register (CD7:0).
During AD1845 initialization, the PIO Playback Data Register cannot be written to and the Capture Data Register is always read
as “1000 0000 (80h).”
CD7:0
PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data
transfers.
The reading of this register will increment the capture byte state machine so that the following read will be from
the next appropriate byte in the sample. The exact byte which is next to be read can be determined by reading the
Status Register. Once all relevant bytes have been read, the state machine will stay pointed to the last byte of the
sample until a new sample is received from the ADCs. Once this has occurred, the state machine and Status
Register will point to the first byte of the sample.
PD7:0
PIO Playback Data Register. This is the control register where playback data is written during programmed I/O
data transfers.
Writing data to this register will increment the playback byte tracking state machine so that the following write will
be to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this
port are ignored. The state machine is reset when the current sample is sent to the DACs.
INDIRECT CONTROL REGISTER DEFINITIONS
The following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed
by a read/write to the Indexed Data Register (ADR1:0 = 1).
Left Input Control (IXA3:0 = 0)
IXA3:0
Data 7
Data 6
0
LSS1
LIG3:0
Left input gain select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
res
Reserved for future expansion. Always write a zero to this bit.
LMGE
Left Input Microphone Gain Enable. This bit will enable the +20 dB gain of the left MIC input signal.
LSS1:0
Left Input Source Select. These bits select the input source for the left gain stage preceding the left ADC.
LSS1
LSS0
Left Input Source
0
0
Left Line Source Selected
0
1
Left Auxiliary 1 Source Selected
1
0
Left Microphone Source Selected
1
1
Left Line Post-Mixed DAC Output Source Selected
This register’s initial state after reset is “000x 0000.”
Right Input Control (IXA3:0 = 1)
IXA3:0
Data 7
Data 6
1
RSS1
RIG3:0
Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.
res
Reserved for future expansion. Always write a zero to this bit.
RMGE
Right Input Microphone Gain Enable. This bit will enable the +20 dB gain of the right MIC input signal.
RSS1:0
Right Input Source Select. These bits select the input source for the right channel gain stage preceding the right
ADC.
Data 5
Data 4
Data 3
CD6
CD5
CD4
CD3
PD6
PD5
PD4
PD3
Data 5
Data 4
Data 3
LSS0
LMGE
res
LIG3
Data 5
Data 4
Data 3
RSS0
RMGE
res
RIG3
–16–
Data 2
Data 1
Data 0
CD2
CD1
CD0
PD2
PD1
PD0
Data 2
Data 1
Data 0
LIG2
LIG1
LIG0
Data 2
Data 1
Data 0
RIG2
RIG1
RIG0
REV. C