IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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AD1845
Interface Configuration Register (IXA3:0 = 9)
IXA3:0
Data 7
Data 6
9
CPIO
NOTE: Placing the AD1845 in the Mode Change Enable (MCE) state is not required when changing the CEN and PEN bits in this
register.
PEN
Playback Enable. This bit will enable the playback of data in the format selected. The AD1845 will generate
PDRQ and respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Pro-
grammed I/O (PIO) playback mode.
0
Playback disabled (PDRQ and PIO Playback Data Register inactive)
1
Playback enabled
CEN
Capture Enable. This bit will enable the capture of data in the format selected. The AD1845 will generate
CDRQ and respond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO
capture mode.
0
Capture disable (CDRQ and PIO Capture Data Register inactive)
1
Capture enable
SDC
Single DMA Channel. This bit will force both capture and playback DMA requests to occur on the Playback
DMA channel. The Capture DMA CDRQ pin will be LO. This bit will allow the AD1845 to be used with only
one DMA channel. Simultaneous capture and playback cannot occur in this mode. Should both capture and
playback be enabled (CEN=PEN=1) in the mode, only playback will occur. See “Data and Control Transfers” for
further explanation.
0
Dual DMA channel mode
1
Single DMA channel mode
ACAL
Autocalibrate Enable. This bit determines whether the AD1845 performs an autocalibration whenever the Mode
Change Enable (MCE) bit changes from HI to LO. See “Autocalibration” for a description of a complete
autocalibration sequence. Note that an autocalibration is forced whenever the RESET or PWRDWN pin is
asserted LO then transitions HI regardless of the state of the ACAL bit.
0
No autocalibration
1
Autocalibration after mode change
res
Reserved for future expansion. Always write zeros to these bits.
PPIO
Playback PIO Enable. This bit determines whether the playback data is transferred via DMA or PIO.
0
DMA transfers only
1
PIO transfers only
CPIO
Capture PIO Enable. This bit determines whether the capture data is transferred via DMA or PIO.
0
DMA transfers only
1
PIO transfers only
This register’s initial state after reset is “00xx 1000.”
Pin Control Register (IXA3:0 = 10)
IXA3:0
Data 7
Data 6
10
XCTL1
XCTL0
INITD
Disable setting the INIT bit after changing the sample rate in MODE1. Otherwise the INIT bit is set HI for
approximately 200 s after changing the sample rate.
0
INIT bit is enabled
1
INIT bit is disabled
IEN
Interrupt Enable. This bit enables the interrupt pin. The Interrupt Pin will go active HI when the number of
samples programmed in the Base Count Register is reached.
0
Interrupt disabled
1
Interrupt enabled
res
Reserved for future expansion. Always write zeros to these bits.
Data 5
Data 4
Data 3
PPIO
res
res
ACAL
Data 5
Data 4
Data 3
res
res
–20–
Data 2
Data 1
Data 0
SDC
CEN
PEN
Data 2
Data 1
Data 0
res
res
IEN
INITD
REV. C