IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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XCTL1:0
External Control. The state of these bits is reflected on the XCTL1:0 pins of the AD1845.
0
Logic LO on XCTL1:0 pins
1
Logic HI on XCTL1:0 pins
This register’s initial state after reset is “00xx xx00.”
Test and Initialization Register (IXA3:0 = 11)
IXA3:0
Data 7
11
COR
ORL1:0
Overrange Left Detect. These bits indicate the overrange on the left capture channel. These bits change on
a sample-by-sample basis, and are read-only.
ORL1
ORL0
0
0
0
1
1
0
1
1
ORR1:0
Overrange Right Detect. These bits indicate the overrange on the right capture channel. These bits change
on a sample-by-sample basis, and are read-only.
ORR1
ORR0
0
0
0
1
1
0
1
1
DRS
Data Request Status. This bit indicates the current status of the PDRQ and CDRQ pins of the AD1845.
0
CDRQ and PDRQ are presently inactive (LO)
1
CDRQ or PDRQ are presently active (HI)
ACI
Autocalibrate-In-Progress. This bit indicates the state of autocalibration or a recent exit from Mode Change
Enable (MCE). This bit is read-only.
0
Autocalibration is not in progress
1
Autocalibration is in progress or MCE was exited within the last 128 sample periods
PUR
Playback Underrun. This bit is set when the playback FIFO is empty and after the next valid sample has been
played back. If this condition exists, DACZ determines the DAC playback value. In MODE1, DACZ is always set
and returns a midscale value.
COR
Capture Overrun. This bit is set when the capture FIFO is full and an additional sample has been captured. The
sample being read will not be overwritten by the new sample. The new sample will be ignored. This bit changes on
a sample by sample basis.
The occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. The SOUR bit
is the logical OR of the COR and PUR bits. This enables a polling host CPU to detect an overrun/underrun condition while check-
ing other status bits.
This register’s initial state after reset is “0000 0000.”
Miscellaneous Control Register (IXA3:0 = 12)
IXA3:0
Data 7
12
MID
MODE2
ID3:0
AD1845 Revision ID. These four bits define the revision level of the AD1845. The AD1845 will have ID =
“1010.” These bits are read-only.
BUF8
Parallel Interface Bus Transceiver Current Buffer Drive. The AD1845 can be programmed to provide a current
drive of 16 mA or 8 mA.
0
16 mA current drive.
1
8 mA current drive.
res
Reserved for future expansion. Always write 0s to these bits.
REV. C
Data 6
Data 5
Data 4
Data 3
PUR
ACI
DRS
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Less than –1 dB underrange
Between –1 dB and 0 dB underrange
Between 0 dB and +1 dB overrange
Greater than +1 dB overrange
Data 6
Data 5
Data 4
Data 3
res
BUF8
–21–
Data 2
Data 1
Data 0
ORR1
ORR0
ORL1
Data 2
Data 1
Data 0
ID3
ID2
ID1
AD1845
ORL0
ID0