IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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AD1845
MODE2
When the AD1845 is initialized, the MODE2 bit is set to 0, LO, and the AD1845 is register set compatible with
the AD1848 and the AD1846. Setting the MODE2 bit to 1, HI, enables access to the indirect registers 16
through 31 which controls the AD1845 Expanded Mode of operation.
0
MODE1: AD1848, AD1846, and CS4248 mode
1
MODE2: AD1845 enhanced feature mode
MID
Manufacturer ID Bit. This bit is set to 1.
This register’s initial state after reset is “10x0 1010.”
Digital Mix/Attenuation Control Register (IXA3:0 = 13)
IXA3:0
Data 7
13
DMA5
DME
Digital Mix Enable. This bit will enable the digital mix of the ADC’s output with the DAC’s input. When en-
abled, the data from the ADCs are digitally mixed with other data being delivered to the DACs regardless of
whether or not playback is enabled (PEN = 1). If capture is enabled (CEN = 1) and there is a capture overrun
(COR), then the last sample captured before overrun will be used for the digital mix. If playback is enabled
(PEN = 1) and there is a playback underrun (PUR), then a midscale zero will be added to the digital mix data if
DACZ = 1, otherwise, the last valid sample will be repeated.
0
Digital mix disabled (muted)
1
Digital mix enabled
res
Reserved for future expansion. Always write a zero to this bit.
DMA5:0
Digital Mix Attenuation. These bits determine the attenuation of the ADC data that is mixed with the DAC in-
put. Each attenuate step is –1.5 dB ranging from 0 dB to –94.5 dB.
This register’s initial state after reset is “0000 00x0.”
DMA Playback Base Count Registers (IXA3:0 = 14 & 15)
The DMA Base Count Registers in the AD1845 simplify integration of the AD1845 in ISA systems. The ISA DMA controller re-
quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. The programmable DMA Base
Count Registers will allow such interrupts to occur.
The Base Count Registers contain the number of samples to be transferred before an interrupt is generated on the interrupt (INT)
pin. To load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both Base
Count Registers to load into the Current Count Register. Once AD1845 transfers are enabled, each sample transferred causes the
Current Count Register to decrement until zero count is reached. The next sample after zero will generate the interrupt and reload
the Current Count Register with the values in the Base Count Registers. The interrupt is cleared by a write to the Status Register.
The Host Interrupt Pin (INT) will go HI during the sample period in which the Current Count Register underflows.
When using the AD1845 in MODE1 (AD1848 compatible), the Current Count Register is decremented every sample period when
either the PEN or CEN bit is enabled. The Current Count Register is decremented in both PIO and DMA data transfer modes.
Interrupt conditions are generated by Current Count Register underflows in both PIO and DMA transfers.
Program maximum value to the Upper Base Count Register to avoid receiving DMA count interrupts while operating in PIO mode.
By enabling MODE2, the AD1845 Expanded Mode, the playback counter is only decremented when a playback sample transfer occurs.
Upper Base Count Register (IXA3:0 = 14)
IXA3:0
Data 7
14
UB7
UB7:0
Upper Base Count. This byte is the upper byte of the base count register containing the eight most significant bits
of the 16-bit base register. Reads from this register return the same value which was written. The current count
contained in the counters can not be read.
This register’s initial state after reset is “ 0000 0000.”
Data 6
Data 5
Data 4
Data 3
DMA4
DMA3
DMA2
DMA1
Data 6
Data 5
Data 4
Data 3
UB6
UB5
UB4
–22–
Data 2
Data 1
Data 0
DMA0
res
DME
Data 2
Data 1
Data 0
UB3
UB2
UB1
UB0
REV. C