AD1845JPZ Analog Devices Inc, AD1845JPZ Datasheet - Page 25

IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part Number
AD1845JPZ
Description
IC CODEC STEREO 5V 16BIT 68PLCC
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of AD1845JPZ

Resolution (bits)
16 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
81 / 82
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
REV. C
TU7:0
This register’s initial state after reset is “0000 0000.”
FU7:0
This register’s initial state after reset is “0001 1111.”
FL7:0
This register’s initial state after reset is “0100 0000.”
PU
PO
CO
CU
PI
CI
Upper Timer Bits Register (IXA3:0 = 21)
Upper Frequency Select Bits Register (IXA3:0 = 22)
Lower Frequency Select Bits Register (IXA3:0 = 23)
Capture Playback Timer Register (IXA3:0 = 24)
IXA3:0
IXA3:0
IXA3:0
IXA3:0
21
22
23
24
Upper Timer Bits. This byte is the upper byte of the timer register containing the eight most significant bits of the
Upper Frequency Select Bits. This register is accessible when FREN is 1. Writing to this register allows the user
Playback Underrun. This bit is set when the DAC runs out of data and a sample has been missed.
Capture Underrun. This bit is set when the host attempts to read from the capture FIFO when it is empty. Under
Playback Interrupt. This bit indicates that there is an interrupt pending from the playback DMA count registers.
Capture Interrupt. This bit indicates that there is an interrupt pending from the capture DMA count registers.
16-bit register. Reads from this register return the same value which was written. The current timer value con-
tained in the counters cannot be read. The timer counter is determined by the clock source selected (see below).
Input Frequency
24.576 MHz
14.31818 MHz
24.000 MHz
25.000 MHz
33.000 MHz
to program the sampling frequency from 4 kHz to 50 kHz in 1 Hz increments. Writing to the Lower and Upper
Frequency Select Register allows the AD1845 to process audio data using approximately 50,000 different audio
sample rates. One LSB represents exactly one hertz. Selecting frequencies below 4 kHz or above 50 kHz will
result in degraded audio performance. Some common sample rates are listed below:
Quality
Voice
Radio
Tape
CD
DAT
Lower Frequency Select Bits. Writing to the Lower Frequency Select register updates the entire 16-bit frequency register.
Playback Overrun. This bit is set when the host tries to write data into the FIFO and the write was ignored be-
cause the FIFO was full.
Capture Overrun. This bit is set when the ADC has a sample to load into the FIFO, and the data was ignored
because the capture FIFO was full.
these circumstances, the last valid byte is sent to the host.
Data 7
Data 7
Data 7
Data 7
TU7
FU7
FL7
res
Sampling Frequency
8.0 kHz
11.025 kHz
22.05 kHz
44.1 kHz
48.0 kHz
Data 6
Data 6
Data 6
Data 6
TU6
FU6
FL6
TI
Divider
247
144
242
252
333
Data 5
Data 5
Data 5
Data 5
TU5
FU5
FL5
CI
–25–
Timer Counter
FU7:0 (hex)
0010 1011
0101 0110
10.050 s
10.057 s
10.083 s
10.080 s
10.091 s
0001 1111
1010 1100
1011 1011
Data 4
Data 4
Data 4
Data 4
TU4
FU4
FL4
PI
Data 3
Data 3
Data 3
Data 3
TU3
FU3
FL3
CU
FL7:0 (hex)
0100 0000
0001 0001
0010 0010
0100 0100
1000 0000
Data 2
Data 2
Data 2
Data 2
TU2
FU2
FL2
CO
Data 1
default
Data 1
Data 1
Data 1
TU1
FU1
FL1
PO
AD1845
Data 0
Data 0
Data 0
Data 0
TU0
FU0
FL0
PU

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