IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part NumberAD1845JPZ
DescriptionIC CODEC STEREO 5V 16BIT 68PLCC
ManufacturerAnalog Devices Inc
TypeStereo Audio
AD1845JPZ datasheet
 


Specifications of AD1845JPZ

Resolution (bits)16 bNumber Of Adcs / Dacs2 / 2
Sigma DeltaYesDynamic Range, Adcs / Dacs (db) Typ81 / 82
Voltage - Supply, Analog4.75 V ~ 5.25 VVoltage - Supply, Digital4.75 V ~ 5.25 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case68-PLCCSingle Supply Voltage (typ)5V
Single Supply Voltage (min)4.75VSingle Supply Voltage (max)5.25V
Package TypePLCCLead Free Status / RoHS StatusLead free / RoHS Compliant
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Power-Down Control Register (IXA3:0 = 27)
IXA3:0
Data 7
27
ADCPWD
DACPWD
res
Reserved for future expansion. Always write zeros to these bits.
FREN
Frequency Select Register Enable. In MODE2, selecting this bit will turn on the Frequency Select Registers (see
indirect registers 22 and 23) and disable CFS2:0.
0
CFS Active.
1
Frequency Select Registers Active, CFS disabled.
MIXPWD
Mixer Power Down. The DAC and the output mixer are powered down, and the DAC sample clock is turned off.
DACPWD
DAC Power Down. The DAC is powered down and the DAC sample clock is turned off.
ADCPWD
ADC Power Down. The ADC is powered down and the ADC sample clock is turned off.
This register’s initial state after reset is “000x 0xxx.”
Capture Data Format Control Register (IXA3:0 = 28)
IXA3:0
Data 7
28
CFMT1
CFMT0
NOTE: Changing CFMT[1:0], CC/L, CS/M, requires the Mode Change Enable (MCE) state or setting CEN = 0.
res
Reserved for future expansion. Always write zeros to these bits.
CS/M
Capture Stereo/Mono Select. Setting this bit determines how the captured audio data will be formatted. In the
Mono mode, valid information is captured on the “left” channel, and the “right” channel data is not valid.
0
Mono Format
1
Stereo Format
CC/L
Capture Companding/Linear Select. This bit is set to determine linear, -Law or A-Law companding. See Figure
12 for CFMT[1:0] and CC/L bit settings that determine the audio data type capture format.
CFMT[1:0]
Capture Data Format. This bit is set to format the data being captured in MODE 2. See Figure 12 for CFMT
and CC/L bit settings that determine the capture audio data type format.
This register’s initial state after reset is “0000 xxxx.”
CFMT1
CFMT0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Crystal, Clock Select/Total Power-Down Register (IXA3:0 = 29)
IXA3:0
Data 7
29
XFS2
TOTPWD
Total Power Down. When TOTPWD = HI, the ADC, DAC, mixer, and voltage reference are powered down, and
the ADC and DAC sample clocks are turned off. Only the digital interface remains active to allow the host to exit
the AD1845 from the total power-down state.
res
Reserved for future expansion. Always write zeros to these bits.
REV. C
Data 6
Data 5
Data 4
Data 3
res
MIXPWD
Data 6
Data 5
Data 4
CC/L
CS/M
CC/L
Audio Data Type
0
Linear, 8-Bit Unsigned PCM
1
-Law, 8-Bit Companded
0
Linear, 16-Bit Twos Complement PCM Little Endian
1
A-Law, 8-Bit Companded
0
Reserved
1
Reserved
0
Linear, 16-Bit Twos-Complement Big Endian
1
Reserved
Figure 12. Capture Audio Data Type
Data 6
Data 5
Data 4
Data 3
XFS1
XFS0
res
–27–
Data 2
Data 1
Data 0
res
res
FREN
Data 3
Data 2
Data 1
res
res
res
Data 2
Data 1
Data 0
res
res
res
TOTPWD
AD1845
res
Data 0
res