AD1845JPZ Analog Devices Inc, AD1845JPZ Datasheet - Page 33

IC CODEC STEREO 5V 16BIT 68PLCC

AD1845JPZ

Manufacturer Part Number
AD1845JPZ
Description
IC CODEC STEREO 5V 16BIT 68PLCC
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of AD1845JPZ

Resolution (bits)
16 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
81 / 82
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
4.75 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.75V
Single Supply Voltage (max)
5.25V
Package Type
PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The AD1845 performs a sequenced power-down that eliminates
audible effects from the DAC’s output, and saves the codec’s
internal operating state. Clearing the bits (writing a “0” to the
control bits) returns the AD1845 from the power-down state
and begins the initialization sequence. The AD1845 exits the
power-down mode within 1 sample period. However, an
additional 128 sample periods are required to unmute the out-
puts and restore the internal settings to the pre-Power-Down
operating state.
• Standby: Entering the Standby mode places the ADC, DAC
• Mixer Power-Down: Entering the Mixer Power-Down mode,
• Mixer Only: The Mixer Only mode is initiated by powering
• ADC Power-Down: Entering the ADC Power-Down mode,
• DAC Power-Down: Entering the DAC Power-Down mode
AUTOCALIBRATION
The AD1845 calibrates the ADCs and DACs for greater accu-
racy by minimizing dc offsets. Upon power-up or after RESET,
the AD1845 automatically performs an autocalibration after the
first return from the Mode Change Enable state, regardless of
the state of the ACAL bit. Autocalibration can be forced when
the AD1845 returns from the Mode Change Enable state and
the ACAL bit in the Interface Configuration register has been
set. If the ACAL bit is not set, the RAM normally containing
ADC and DAC offset compensations will be saved, retaining
the offsets of the most recent autocalibration.
The completion of autocalibration can be determined by polling
the Autocalibrate-In-Progress (ACI) bit in the Test and Initial-
ization Register, which will be set during autocalibration. Trans-
fers enabled during autocalibration do not begin until the
completion of autocalibration.
The following summarizes the procedure for autocalibration:
• Set the Mode Change Enable (MCE) bit.
• Set the Autocalibration (ACAL) bit.
REV. C
and the Mixer into a low power state, and forces all outputs
to be muted. Standby turns off all internal digital and analog
circuitry with the exception of the digital interface and the
voltage reference. All ADC and DAC data is flushed includ-
ing data in the capture and playback FIFOs.
causes both the mixer and the DAC circuitry to be turned
off. All DAC data is flushed including data in the playback
FIFO. In this mode the mixer is off and the AD1845 is
muted, but the ADC remains functional.
down both the ADC and DAC, leaving the analog mixer and
the digital interface active. MIC, LINE, AUX1, AUX2, and
M_IN can be mixed in the analog domain on the AD1845
outputs. All ADC and DAC data is flushed including data in
the capture and playback FIFOs.
causes the ADC digital and analog engines to be turned off.
All ADC data is flushed including data in the capture FIFO
and the AD1845 is rendered deaf. The input programmable
gain amplifier (PGA) is also shut down. The DAC and
mixer remain active allowing the AD1845 to continue to
playback and mix samples.
suspends the DAC digital and analog engines, and all DAC
data is flushed including data in the playback FIFO. How-
ever, the mixer and ADC are functional allowing the
AD1845 to continue to capture and mix samples.
–33–
• Clear the Mode Change Enable (MCE) bit.
• The Autocalibrate-In-Progress (ACI) bit will remain HI for
• Set desired gain/attenuation/mute and digital mix values.
During the autocalibration sequence, data output from the
ADCs is meaningless. Inputs to the DACs are ignored. Even if
the user specified the muting of all analog outputs, near the end
of the autocalibration sequence, dc analog outputs very close to
V
CHANGING SAMPLE RATES
In MODE1 the AD1845 can change sample rates by entering
the Mode Change Enable state or writing directly to the Clock
and Data Format Register. In MODE2, the AD1845 changes
sample rates by writing directly to the Upper and Lower Fre-
quency Select Register. Please refer to the following examples
for changing the sample rate.
To change the selection of the current sample rate by entering
the Mode Change Enable state requires the sequence which is
summarized as follows (this is the same sequence used by the
AD1848, AD1846, CS4248, and CS4231):
Alternatively, the AD1845 can be programmed to change the
sample rate selection “on the fly” without entering the Mode
Change Enable Sequence. The following sequence applies to
the AD1845 operating in MODE1 or MODE2.
• Set the Mode Change Enable (MCE) bit.
• In a single write cycle, change the Clock Frequency Divide
• The AD1845 now needs to resynchronize its internal states to
• Clear the Mode Change Enable (MCE) bit.
• If ACAL is set, follow the procedure described in
• Wait 128 sample cycles or poll the ACI bit until it transitions
• Set to desired gain/attenuation values, and unmute DAC
• In a single write cycle, change the Clock Frequency Divide
• The AD1845 now needs to resynchronize its internal states to
• Set to desired gain/attenuation values, and unmute DAC
REF
Select (CFS2:0) and/or the Clock Source Select (CSS).
the new clock. Writes to the AD1845 will be ignored. Reads
will produce “1000 0000 (80h)” until the resynchronization is
complete. Poll the Index Register until something other than
this value is returned.
“Autocalibration” above.
LO.
outputs (if muted).
Select (CFS2:0) and/or the Clock Source Select (CSS). For
compatibility reasons, the AD1845 will send out “1000 0000
(80h)” for approximately 200 s. Even this short wait can be
disabled by setting the INITD bit. When the INITD bit is set,
the AD1845 is ready immediately after changing the sample
rate using CFS and CSS.
the new clock. Writes to the AD1845 will be ignored. Reads
will produce “1000 0000 (80h)” until the resynchronization is
complete. Poll the Index Register until something other than
this value is returned.
outputs (if muted).
384 sample periods. Poll the ACI bit until it transitions from
HI to LO.
will be produced at the line output.
AD1845

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