ETC5054N/H STMicroelectronics, ETC5054N/H Datasheet - Page 7

• Manufacturer Part Number: ETC5054N/H
• Description: IC CODEC/FILTER SERIAL 16-DIP
• Manufacturer: STMicroelectronics
• Type: PCM Codec/Filterr

Specifications of ETC5054N/H

• Data Interface: Serial
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1339-5

TIMING SPECIFICATIONS
Note 1: For short frame sync timing FS
Figure 1: 64kbits/s TIMING DIAGRAM (see next page for complete timing).
Symbol
t
t
1/t
t
t
t
t
t
SBFM
t
t
t
t
t
t
t
HOLD
t
t
WMH
WML
t
t
WBH
HBFI
t
WBL
t
t
DBD
DZC
SDB
HBD
t
t
XDP
WFL
HBF
SFB
DZF
RM
FM
PB
RB
HF
FB
SF
PM
FSx
FS
R
Frequency of master clocks
Depends on the device used and the BCLK
Width of Master Clock High
Width of Master Clock Low
Rise Time of Master Clock
Fall Time of Master Clock
Period of Bit Clock
Width of Bit Clock High (V
Width of Bit Clock Low (V
Rise Time of Bit Clock (t
Fall Time of Bit Clock (t
Set-up time from BCLK
(first bit clock after the leading edge of FS
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
Set-up Time from Frame Sync to Bit Clock (long frame only)
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
Delay time to valid data from FS
and delay time from FS
(C
Delay time from BCLK
(load = 150pF plus 2 LSTTL loads)
Delay time from BCLK
Set-up time from D
Hold time from BCLK
Holding Time from Bit Clock High to Frame Sync
(short frame only)
Set-up Time from FS
(short frame sync pulse) - Note 1
Hold Time from BCLK
(short frame sync pulse) - Note 1
Delay Time to TS
Minimum Width of the Frame Sync Pulse (low level)
64kbit/s operating mode)
L
= 0pF to 150pF)
X
low (load = 150pF plus 2 LSTTL loads)
R
X
and FS
valid to BCLK
X/R
R/X
X/R
X
X
X
PB
X
high to data valid.
low to data output disabled.
PB
to BCLK
low to D
high to MCLK
to data output disabled.
Low to FS
IL
IH
= 488ns)
R
= 488ns)
= 0.6V)
Parameter
must go high while their respective bit clocks are high.
= 2.2V)
X
R
X/R
or BCLK
R/X
invalid.
X/R
Low
MCLK
low.
X
Low
falling edge.
X
X
)
R
, whichever comes later
X
/CLKSEL Pin
and MCLK
MCLK
MCLK
MCLK
MCLK
X
X
X
X
FS
R
and MCLK
and MCLK
and MCLK
and MCLK
X
or FS
R
R
R
R
R
Min.
160
160
485
160
160
100
100
100
160
80
20
50
50
50
80
0
0
0
ETC5054 - ETC5057
1.536
1.544
2.048
Typ.
488
15.725
Max.
165
180
165
140
50
50
50
50
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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