ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet
ENC424J600-I/ML
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ENC424J600-I/ML Summary of contents
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... Stand-Alone 10/100 Ethernet Controller 2010 Microchip Technology Inc. ENC424J600/624J600 Data Sheet with SPI or Parallel Interface DS39935C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... ENC624J600 24K 64 10/100 2010 Microchip Technology Inc. ENC424J600/624J600 • Security Engines: - High-performance, modular exponentiation engine with up to 1024-bit operands - Supports RSA exchange algorithms - High-performance AES encrypt/decrypt engine with 128-bit, 192-bit or 256-bit key - Hardware AES ECB, CBC, CFB and OFB ...
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... ENC424J600/624J600 Pin Diagrams 44-Pin TQFP and QFN CS/CS SO/WR/EN SI/RD/RW SCK/AL AD0 AD1 AD2 AD3 CAP V DD DS39935C-page ENC424J600 SSTX TPOUT- TPOUT+ V SSTX V DDTX TPIN- TPIN+ V DDRX V SSRX V SSPLL V DDPLL 2010 Microchip Technology Inc. ...
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... Pin Diagrams (Continued) 64-Pin TQFP CS/CS SO/WR/WRL/EN/B0SEL SI/RD/RW SCK/AL/PSPCFG4 AD0 AD1 AD2 AD3 CAP V DD 2010 Microchip Technology Inc. ENC424J600/624J600 ENC624J600 SSTX 31 TPOUT- 30 TPOUT SSTX 28 V DDTX TPIN TPIN DDRX 24 V SSRX V 23 SSPLL 22 V DDPLL A11 19 A10 18 PSPCFG3 17 PSPCFG2 ...
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... ENC424J600/624J600 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 External Connections ................................................................................................................................................................... 9 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 39 5.0 Parallel Slave Port Interface (PSP) ............................................................................................................................................ 51 6.0 Ethernet Overview ...................................................................................................................................................................... 71 7.0 Reset .......................................................................................................................................................................................... 73 8.0 Initialization................................................................................................................................................................................. 75 9.0 Transmitting and Receiving Packets .......................................................................................................................................... 83 10.0 Receive Filters............................................................................................................................................................................ 95 11.0 Flow Control ............................................................................................................................................................................. 105 12 ...
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... Fast Ethernet controllers with an industry standard Serial Peripheral Interface (SPI flexible parallel interface. They are designed to serve as an Ethernet network interface for any microcontroller equipped with SPI or a standard parallel port. ENC424J600/624J600 devices meet all of the IEEE 802.3 specifications applicable to 10Base-T and 100Base-TX Ethernet, including clauses, such as auto-negotiation ...
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... ENC424J600/624J600 FIGURE 1-1: ENC424J600/624J600 BLOCK DIAGRAM Bus I/O Interface Interface SO CS/CS SCK/AL SI/RD/RW (1) AD<15:0> (1) A<14:0> WR/WRL/ (1) EN/B0SEL WRH/ Control (1) B1SEL Registers (1) PSPCFGx SPISEL Control Logic LEDA LEDB INT Note 1: A<14:0>, AD15, WRL/B0SEL, WRH/B1SEL and PSPCFG<4:1> are available on 64-pin devices only. PSPCFG0 is available on 44-pin devices only ...
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... TABLE 1-2: ENC424J600/624J600 PINOUT DESCRIPTIONS Pin Number Pin Name Pin Type 44-Pin 64-Pin AD0 38 53 AD1 39 54 AD2 40 55 AD3 41 56 AD4 5 5 AD5 6 6 AD6 7 7 AD7 8 8 AD8 25 35 AD9 26 36 AD10 27 37 AD11 28 38 AD12 29 39 AD13 30 40 ...
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... ENC424J600/624J600 TABLE 1-2: ENC424J600/624J600 PINOUT DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Type 44-Pin 64-Pin OSC1 3 3 OSC2 2 2 PSPCFG0 32 — PSPCFG1 — 45 PSPCFG2 — 17 PSPCFG3 — 18 PSPCFG4 — 52 RBIAS SCK SPISEL 24 34 TPIN TPIN TPOUT TPOUT CAP V 44 21, 47 DDOSC ...
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... M F approx. 3: The load capacitors’ value should be derived from the capacitive loading specification provided by the crystal manufacture. 2010 Microchip Technology Inc. ENC424J600/624J600 FIGURE 2-2: designed to 3.3V Clock from External System Open Note 1: Duty cycle restrictions must be observed. ...
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... ENC424J600/624J600 2.3 Voltage and Bias Pin 2.3.1 V AND V PINS reduce on-die noise levels and provide for the high-current demands of Ethernet, there are many power pins on ENC424J600/624J600 devices: • V and • V and V DDOSC SSOSC • V and V DDPLL SSPLL • V and V DDRX SSRX • ...
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... Ethernet Signal Pins and External Magnetics Typical applications for ENC424J600/624J600 devices require an Ethernet transformer module, and a few resistors and capacitors to implement a complete IEEE 802.3 compliant 10/100 Ethernet interface, as shown in Figure 2-5. The Ethernet transmit interface consists of two pins: TPOUT+ and TPOUT-. These pins implement a differential pair and a current-mode transmitter ...
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... ENC424J600/624J600 2.4.1 ADDITIONAL EMI AND LAYOUT CONSIDERATIONS To reduce EMI emissions, common-mode chokes are shown adjacent to the transformers on the cable (RJ-45) side. These chokes come standard in typical Ethernet transformer modules. ENCX24J600 PHY uses a current-mode drive topol- ogy, the transmit choke must normally be located on the cable side of the transmit transformer ...
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... SPISEL pin function is being used. Since ENC424J600/624J600 devices incorporate a buffer for storing transmit and receive packets, the host microcontroller never needs to perform real-time operations on the device. The microcontroller can poll the device registers to discover if the device status has changed ...
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... SPISEL pin. The combinations of V ages on the different PSPCFG mode pins determine the PSP mode according to Table 2-1. On ENC424J600 devices, only PSP Modes 5 and 6 (8-bit width, multiplexed data and address) are available. The mode is selected by applying respectively, to PSPCFG0 ...
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... V unloaded. 2.8 Digital I/O Levels All digital output pins on ENC424J600/624J600 devices contain CMOS output drivers that are capable of sinking and sourcing continuously. All digital inputs and I/O pins operating as inputs are 5V tolerant. These features generally mean that the ENCX24J600 can connect directly to the host microcontroller without the need of any glue logic ...
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... ENC424J600/624J600 NOTES: DS39935C-page 16 2010 Microchip Technology Inc. ...
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... MEMORY ORGANIZATION All memory in ENC424J600/624J600 devices is implemented as volatile RAM. Functionally, there are four unique memories: • Special Function Registers (SFRs) • PHY Special Function Registers • Cryptographic Data Memory • SRAM Buffer The SFRs configure, control and provide status information for most of the device. They are directly accessible through the I/O interface ...
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... PSP bus. As with the serial inter- face, the cryptographic memory can only be accessed through the DMA. FIGURE 3-2: ENC424J600/624J600 MEMORY MAPS FOR PSP INTERFACES 8-Bit PSP Main Area PSP Address Bus and All Pointers ...
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... MAC register, the low byte of a second MAC register and then the high byte of the first register cannot be performed. 2010 Microchip Technology Inc. ENC424J600/624J600 3.2.3 SPI REGISTER MAP As previously described, the SFR memory is partitioned into four banks plus a special region that is not bank addressable ...
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... ENC424J600/624J600 TABLE 3-1: ENC424J600/624J600 SFR MAP (SPI INTERFACE) Bank 0 Bank 1 (00h offset) (20h offset) Name 00 00 ETXSTL ETXSTH ETXLENL ETXLENH ERXSTL ERXSTH ERXTAILL ERXTAILH ERXHEADL ERXHEADH EDMASTL EDMASTH EDMALENL EDMALENH EDMADSTL EDMADSTH EDMACSL EDMACSH ETXSTATL ETXSTATH ETXWIREL ETXWIREH 35 ERXFCONH 16 16 EUDASTL ...
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... SPI interface, the EUDAST, EUDAND, ESTAT, EIR and ECON1 registers are instantiated in four locations in the PSP memory maps. Users may opt to use any one of these four locations. TABLE 3-2: ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 8-BIT PSP INTERFACE) Addr Name Addr Name 7E00 ...
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... ENC424J600/624J600 TABLE 3-3: ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 16-BIT PSP INTERFACE) Addr Name Addr Name 3F00 ETXST 3F10 EHT1 3F01 ETXLEN 3F11 EHT2 3F02 ERXST 3F12 EHT3 3F03 ERXTAIL 3F13 EHT4 3F04 ERXHEAD 3F14 EPMM1 3F05 EDMAST 3F15 EPMM2 3F06 ...
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... TABLE 3-4: ENC424J600/624J600 SFR MAP (SET REGISTER MAP, 8-BIT PSP INTERFACE) (1) Bit Set Registers (7F00h to 7F7Fh) Addr Name Addr 7F00 ETXSTSETL 7F20 7F01 ETXSTSETH 7F21 7F02 ETXLENSETL 7F22 7F03 ETXLENSETH 7F23 7F04 ERXSTSETL 7F24 7F05 ERXSTSETH 7F25 7F06 ERXTAILSETL 7F26 7F07 ...
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... ENC424J600/624J600 TABLE 3-5: ENC424J600/624J600 SFR MAP (CLR REGISTER MAP, 8-BIT PSP INTERFACE) (1) Bit Clear Registers (7F80h to 7FFFh) Addr Name Addr 7F80 ETXSTCLRL 7FA0 7F81 ETXSTCLRH 7FA1 7F82 ETXLENCLRL 7FA2 7F83 ETXLENCLRH 7FA3 7F84 ERXSTCLRL 7FA4 7F85 ERXSTCLRH 7FA5 7F86 ERXTAILCLRL 7FA6 ...
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... TABLE 3-6: ENC424J600/624J600 SFR MAP (SET/CLR REGISTER MAP, 16-BIT PSP INTERFACE) (1) Bit Set Registers (3F80h to 3FBFh) Addr Name Addr 3F80 ETXSTSET 3F90 3F81 ETXLENSET 3F91 3F82 ERXSTSET 3F92 3F83 ERXTAILSET 3F93 3F84 — 3F94 3F85 EDMASTSET 3F95 3F86 EDMALENSET 3F96 3F87 ...
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... TABLE 3-7: ENC424J600/624J600 REGISTER FILE SUMMARY High Byte (‘H’ Register) 8-Bit File Bit 7 Bit 6 Bit 5 Bit 4 Name 16-Bit Bit 15 Bit 14 Bit 13 Bit 12 EUDAST — User-Defined Area Start Pointer (EUDAST<14:8>) EUDAND — User-Defined Area End Pointer (EUDAND<14:8>) ESTAT INT FCIDLE RXBUSY ...
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... TABLE 3-7: ENC424J600/624J600 REGISTER FILE SUMMARY (CONTINUED) High Byte (‘H’ Register) 8-Bit File Bit 7 Bit 6 Bit 5 Bit 4 Name 16-Bit Bit 15 Bit 14 Bit 13 Bit 12 MICMD — — — — MIREGADR — — — r MAADR3 MAC Address, Byte 6 (MAADR<7:0>) MAADR2 MAC Address, Byte 4 (MAADR<23:16>) MAADR1 MAC Address, Byte 2 (MAADR< ...
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... ENC424J600/624J600 3.3 PHY Special Function Registers The PHY registers provide configuration and control of the PHY module, as well as status information about its operation. These 16-bit registers are located in their own memory space, outside of the main SFR space. Unlike other SFRs, the PHY SFRs are not directly accessible through the SPI or PSP interfaces ...
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... PHREG<4:0>: MII Management PHY Register Address Select bits The address of the PHY register which MII Management read and write operations will apply to. 2010 Microchip Technology Inc. ENC424J600/624J600 After setting the MIISCAN bit, the MIRD register will automatically be updated every 25.6 s. There is no status information which can be used to determine when the MIRD registers are updated ...
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... ENC424J600/624J600 REGISTER 3-2: MICMD: MII MANAGEMENT COMMAND REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 MIISCAN: MII Scan Enable bit 1 = PHY register designated by MIREGADR< ...
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TABLE 3-9: PHY REGISTER FILE SUMMARY File Name Bit 15 Bit 14 Bit 13 Bit 12 PHCON1 PRST PLOOPBK SPD100 ANEN PSLEEP PHSTAT1 r FULL100 HALF100 FULL10 PHANA ADNP r ADFAULT r ADPAUS1 ADPAUS0 PHANLPA LPNP LPACK LPFAULT r LPPAUS1 ...
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... ENC424J600/624J600 3.4 Cryptographic Data Memory The cryptographic data memory is used to store key and data information for the Modular Exponentiation, AES and MD5/SHA-1 hashing engines. The RAM for these modules is actually implemented inside of the modules themselves; this allows fast memory access for the access-intensive encryption engines, as well as the simultaneous use of more than one module by an application ...
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... Ethernet frames, or any combination of numerous smaller packets. 2010 Microchip Technology Inc. ENC424J600/624J600 The host controller may only program the ERXST Pointer when the receive logic is disabled. The pointer must not be modified while the receive logic is enabled by having RXEN (ECON1< ...
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... ENC424J600/624J600 3.5.5 INDIRECT SRAM BUFFER ACCESS Indirect access to the SRAM buffer is available to all I/O interfaces. For the SPI interface the only method available. For PSP interfaces, it may be used in addition to the direct access method. Three separate pointer pairs are available for the host microcontroller to use when accessing the SRAM: • ...
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... EGPRDPT/EGPWRPT = 0000h else if EGPRDPT/EGPWRPT = 5FFFh, then EGPRDPT/EGPWRPT = 0000h else EGPRDPT/EGPWRPT = EGPRDPT/EGPWRPT + 1 2010 Microchip Technology Inc. ENC424J600/624J600 3.5.5.1 Circular Wrapping with EGPDATA Normally, operations involving EGPDATA cause the EGPRDPT or EGPWRPT Pointer to automatically increment by one byte address. However, if the end of the general purpose buffer area (ERXST – ...
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... ENC424J600/624J600 3.5.5.2 Circular Wrapping with ERXDATA As with the general purpose pointers, operations with ERXDATA normally cause the ERXWRPT Pointer to automatically increment by one byte address. However, if the end of the receive buffer area (5FFFh) is reached, the pointer will increment to the start of the receive FIFO buffer area instead, as defined by ERXST (Figure 3-7) ...
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... Unimplemented Case 1: EUDAND > EUDAST Normal User-Defined Buffer 2010 Microchip Technology Inc. ENC424J600/624J600 user-defined area pointers will jump over the range of addresses between EUDAND and EUDAST. This is shown in Case 2. If the user-defined buffer is not needed, it can effectively be disabled by setting EUDAST and EUDAND to addresses outside of the implemented memory area ...
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... ENC424J600/624J600 NOTES: DS39935C-page 38 2010 Microchip Technology Inc. ...
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... An SPI port is commonly available on many micro- controllers, and can be simulated in software on regular I/O pins where it is not implemented. This makes the SPI port ideal for using ENC424J600/624J600 devices with the widest possible range of host controllers. 4.1 Physical Implementation The SPI port on ENC424J600/624J600 devices operates as a slave port only ...
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... ENC424J600/624J600 TABLE 4-1: SPI INSTRUCTION SET Instruction Bank 0 Select Bank 1 Select Bank 2 Select Bank 3 Select System Reset Flow Control Disable Flow Control Single Flow Control Multiple Flow Control Clear Decrement Packet Counter DMA Stop DMA Start Checksum DMA Start Checksum with Seed ...
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... SCK Hi-Z x 2010 Microchip Technology Inc. ENC424J600/624J600 4.3.1 BxSEL OPCODES The bank select opcodes, B0SEL, B1SEL, B2SEL and B3SEL, switch the SFR bank to Bank 0, Bank 1, Bank 2 or Bank 3, respectively. The updated bank select state is saved internally inside the ENCX24J600 in volatile memory ...
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... ENC424J600/624J600 TABLE 4-2: SINGLE BYTE INSTRUCTIONS Mnemonic Opcode 1100 0000 Selects SFR Bank 0 B0SEL 1100 0010 Selects SFR Bank 1 B1SEL 1100 0100 Selects SFR Bank 2 B2SEL 1100 0110 Selects SFR Bank 3 B3SEL 1100 1010 Issues System Reset by setting ETHRST (ECON2<4>) SETETHRST 1110 0000 Disables flow control (sets ECON1< ...
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... Microchip Technology Inc. ENC424J600/624J600 For write commands (shown in Figure 4-4), the opcode byte (‘011xxx00’) must be presented on the SI line, MSb first, followed immediately by the pointer data to be written. Like the data returned during a read operation, the write data must be presented MSb first, Least Significant Byte first ...
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... ENC424J600/624J600 TABLE 4-3: THREE-BYTE INSTRUCTIONS Opcode Mnemonic 1st Byte 2nd Byte 0110 0000 dddd dddd DDDD DDDD Write General Purpose Buffer Read Pointer WGPRDPT 0110 0010 xxxx xxxx XXXX XXXX Read General Purpose Buffer Read Pointer RGPRDPT 0110 0100 dddd dddd DDDD DDDD Write Receive Buffer Read Pointer (ERXRDPT). ...
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... Microchip Technology Inc. ENC424J600/624J600 bank prior to their execution. Because of this, they cannot be used for the unbanked SFR space (80h through 9Fh). Figure 4-5 shows the timing relationships for these operations. Like all other opcodes, data must be presented on the SI pin, MSb first. For all banked ...
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... ENC424J600/624J600 There are four banked SFR opcodes, summarized in Table 4-4. Additional details for these opcodes are provided below. 4.6.1.1 WCR Opcode The Write Control Register (WCR) opcode byte consists of the prefix, ‘010’, concatenated with the 5-bit banked SFR address of the first register to write to. For ...
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... Microchip Technology Inc. ENC424J600/624J600 byte-wise on SO, MSb first. As with three-byte instructions, the lower byte of a data word is presented first, followed by the upper byte. As long as the CS pin is held low, the instruction continues to execute, automatically incrementing to the next register address in the SFR space and writing data from SI to, or outputting data on SO from, subsequent registers ...
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... ENC424J600/624J600 4.6.2.1 WCRU Opcode The Write Control Register Unbanked (WCRU) opcode starts with the opcode, ‘00100010’ (22h), followed by the unbanked SFR register address during SPI clocks, 9 through 16. For example, to write to ECON2L at address 6Eh, the instruction would be ‘22h 6Eh’, followed by the data to be written. ...
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... Microchip Technology Inc. ENC424J600/624J600 SO during SCK clocks, 1 through 8. Starting with the 9th clock, data is clocked out byte-wise on SO, MSb first. As long as the CS pin is held low, the instruction continues to execute, automatically incrementing to the next SRAM address according to the pointer wrapping rules described in Section 3.5.5 “ ...
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... ENC424J600/624J600 TABLE 4-6: N-BYTE SRAM INSTRUCTIONS Instruction Read Data from EGPDATA Write Data from EGPDATA Read Data from ERXDATA Write Data from ERXDATA Read Data from EUDADATA Write Data from EUDADATA Legend: x/X = read data (LSB/MSB), d/D = write data (LSB/MSB). ‘X’ and ‘D’ are optional. ...
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... Note 1: Includes only address, data and port control strobes. INT/SPISEL and PSPCFG pins used for mode configuration are not included. 2010 Microchip Technology Inc. ENC424J600/624J600 tieing each of the PSPCFG<4:0> pins to either The available combinations along with relative SS performance metrics are summarized in Table 5-1. ...
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... ENC424J600/624J600 5.2 Using the PSP Interface Unlike the serial interface, the PSP interface does not use opcodes or a command architecture to control the device. Instead, the memory space is accessed directly using the addressing schemes Section 3.1.2 “PSP Interface Maps”. Control SFRs are read and written to directly, or manipulated through their accompanying Bit Set and Bit Clear registers ...
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... Each of the modes is described in detail in the following sections. 2010 Microchip Technology Inc. ENC424J600/624J600 5.3.1 MODE 1 PSP Mode 8-bit, fully demultiplexed mode that is available on 64-pin devices only. The parallel inter- face consists of 8 bi-directional data pins (AD<7:0>) and separate address pins (A< ...
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... ENC424J600/624J600 FIGURE 5-1: DEVICE CONNECTIONS FOR PSP MODE 1 Host MCU PMA<14:9> PMA<8:0> PMD<7:0> Note 1: Use of the CS strobe from the controller is optional. If not used, tie Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V addressing is desired. 3: Use of the external interrupt signal to the controller is optional. ...
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... Note 1: Use of the CS strobe from the controller is optional. If not used, tie Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V addressing is desired. 3: Use of the external interrupt signal to the controller is optional. 2010 Microchip Technology Inc. ENC424J600/624J600 To perform a read operation: 1. Raise the CS line (if connected to the host). 2. ...
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... ENC424J600/624J600 FIGURE 5-5: MODE 2 READ OPERATION TIMING (TWO BYTES PSP1 A<14:0> AD<7:0> Hi-Z FIGURE 5-6: MODE 2 WRITE OPERATION TIMING (TWO BYTES PSP5 R/W EN A<14:0> T PSP6 AD<7:0> Hi-Z T PSP7 DS39935C-page 56 T PSP4 Address<14:0> Address<14:0> Data<7:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address<14:0> ...
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... Use of the external interrupt signal to the controller is optional. 2010 Microchip Technology Inc. ENC424J600/624J600 When RD is raised high, the data bus begins driving out indeterminate data for a brief period, then switches to the correct read data after the appropriate read access time has elapsed ...
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... ENC424J600/624J600 FIGURE 5-8: MODE 3 READ OPERATION TIMING (FOUR BYTES PSP1 WRL WRH A<13:0> Address<13:0> AD<15:0> Hi-Z FIGURE 5-9: MODE 3 WRITE OPERATION TIMING (THREE BYTES PSP5 RD WRL WRH A<13:0> T PSP6 AD<15:0> Hi-Z T PSP7 DS39935C-page 58 T PSP4 Address<13:0> Data<15:0> Hi PSP2 PSP3 T T PSP8 PSP11 Address< ...
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... Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V addressing is desired. 4: Use of the external interrupt signal to the controller is optional. 2010 Microchip Technology Inc. ENC424J600/624J600 4. Raise one or both byte select strobes. When either BxSEL pin is raised high, the data bus ...
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... ENC424J600/624J600 FIGURE 5-11: MODE 4 READ OPERATION TIMING (FOUR BYTES) CS R/W B0SEL T PSP1 B1SEL A<13:0> AD<15:0> Hi-Z FIGURE 5-12: MODE 4 WRITE OPERATION TIMING (THREE BYTES PSP5 R/W B0SEL B1SEL A<13:0> T PSP6 AD<15:0> Hi-Z T PSP7 DS39935C-page 60 T PSP4 Address<13:0> Address<13:0> Data<15:0> Hi PSP2 PSP3 ...
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... Selecting PSP Mode 5 differs between 44-pin and 64-pin devices, as shown in Figure 5-13. For the 44-pin ENC424J600, tie PSPCFG0 For the 64-pin SS ENC624J600, tie PSPCFG1 and PSPCFG2 to V and PSPCFG3 to V ...
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... PMALL 6 AD<14:9> PMA<14:9> PMA8 AD8 8 AD<7:0> PMD<7:0> (3) INT/SPISEL INTx 100 k PSPCFG0 CS PMCSx RD PMRD WR PMWR AL PMALL 6 AD<14:9> PMA<14:9> PMA8 AD8 8 AD<7:0> PMD<7:0> (3) INT/SPISEL INTx +3.3V 100 k PSPCFG1 PSPCFG2 PSPCFG3 ENC424J600 (1) (2) ENC624J600 (1) ( when only indirect DD 2010 Microchip Technology Inc. ...
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... AL T PSP13 (1) AD<14:9> Address<14:9> (1) AD8 Address<8> AD<7:0> Hi-Z Address<7:0> T PSP12 Note 1: AD8 must be driven by the host controller. AD<14:9> may be tied to logic high when only indirect access is desired. 2010 Microchip Technology Inc. ENC424J600/624J600 T PSP4 T PSP15 Data<7:0> Hi PSP2 PSP3 T PSP14 T T PSP8 PSP11 Data< ...
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... Selecting PSP Mode 6 differs between 44-pin and 64-pin devices, as shown in Figure 5-16. For the 44-pin ENC424J600, tie PSPCFG0 For the 64-pin DD ENC624J600, tie PSPCFG1 and PSPCFG3 to V and PSPCFG2 to V ...
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... ENC424J600/624J600 PMCSx PMRD/PMWR PMENB PMALL 6 PMA<14:9> PMA8 8 PMD<7:0> (3) INTx +3.3V 100 k PMCSx PMRD/PMWR PMENB PMALL 6 PMA<14:9> PMA8 8 PMD<7:0> (3) INTx +3.3V 100 k ENC424J600 ( (2) AD<14:9> AD8 AD<7:0> INT/SPISEL PSPCFG0 ENC624J600 ( (2) AD<14:9> AD8 AD<7:0> INT/SPISEL PSPCFG1 PSPCFG2 PSPCFG3 . ...
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... ENC424J600/624J600 FIGURE 5-17: MODE 6 READ OPERATION TIMING (TWO BYTES – SAME ADDRESS PSP12 R PSP13 (1) AD<14:9> Address<14:9> (1) AD8 Address<8> AD<7:0> Hi-Z Address<7:0> T PSP12 Note 1: AD8 must be driven by the host controller. AD<14:9> may be tied to logic high when only indirect access is desired . FIGURE 5-18: MODE 6 WRITE OPERATION TIMING (TWO BYTES – ...
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... Pins” for details. 3: Use of the external interrupt signal to the controller is optional. 2010 Microchip Technology Inc. ENC424J600/624J600 The AD<15:0> bus begins driving out indeterminate data for a brief period, then switches to the correct read data after the appropriate read access time has elapsed. When RD is lowered, the AD< ...
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... ENC424J600/624J600 FIGURE 5-20: MODE 9 READ OPERATION TIMING (FOUR BYTES – SAME ADDRESS PSP12 RD WRL WRH AL T PSP13 AD<15:0> Hi-Z Address<13:0> T PSP12 FIGURE 5-21: MODE 9 WRITE OPERATION TIMING (THREE BYTES – SAME ADDRESS PSP12 RD WRL WRH AL T PSP13 AD<15:0> Hi-Z Address<13:0> T PSP12 ...
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... Use of the external interrupt signal to the controller is optional. 2010 Microchip Technology Inc. ENC424J600/624J600 When either BxSEL pin is raised high, the AD<15:0> bus begins driving out indeterminate data for a brief period, then switches to the correct read data after the appropriate read access time has elapsed. When B0SEL and B1SEL are both low, AD< ...
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... ENC424J600/624J600 FIGURE 5-23: MODE 10 READ OPERATION TIMING (FOUR BYTES – SAME ADDRESS PSP12 R/W B0SEL B1SEL AL T PSP13 AD<15:0> Hi-Z Address<13:0> T PSP12 FIGURE 5-24: MODE 10 WRITE OPERATION TIMING (THREE BYTES – SAME ADDRESS PSP12 R/W B0SEL B1SEL AL T PSP13 AD<15:0> Hi-Z Address< ...
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... ETHERNET OVERVIEW Before discussing the use of ENC424J600/624J600 devices in Ethernet applications, it may be helpful to review the structure of a typical data frame. For more detailed information, refer to IEEE 802.3 Standard, which defines the Ethernet protocol Microchip Application Note AN1120, “Ethernet Theory of Operation”. ...
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... DATA The data field typically consists of between 0 and 1500 bytes of payload data for each frame. ENC424J600/624J600 devices are capable of trans- mitting and receiving frames larger than this when the Huge Frame Enable bit, HFRMEN (MACON2<2>), is set. However, these larger data frames violate Ethernet specifications and will likely be dropped by most Ethernet nodes ...
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... RESET ENC424J600/624J600 differentiates between five types of Resets: • Power-on Reset (POR) • System Reset • Transmit Only Reset • Receive Only Reset • PHY Subsystem Reset A simplified block diagram of the on-chip Reset circuit is shown in Figure 7-1. 7.1 Power-on Reset Power-on Reset occurs when V ...
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... ENC424J600/624J600 7.3 Transmit Only Reset A Transmit Only Reset is performed by setting the TXRST bit (ECON2<6>). The transmit logic is held in Reset until the bit is cleared. Any pending transmission is aborted and TXRTS (ECON1<1>) is cleared. To resume normal operation, clear the TXRST bit. Both the POR and System Resets automatically perform a Transmit Reset, so this step does not need to be per- formed after a System or Power-on Reset ...
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... Reset events. For more information on using the output of the CLKOUT pin, see Section 2.2 “CLKOUT Pin” . 2010 Microchip Technology Inc. ENC424J600/624J600 8.3 Receive Buffer Before packet reception is enabled, the receive buffer must be configured by programming the ERXST Pointer ...
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... ENC424J600/624J600 8.6.1 PREPROGRAMMED MAC ADDRESS As shipped, each ENCX24J600 device has been preprogrammed with a unique MAC address. This value is stored in nonvolatile memory and reloaded into the MAADR registers after every Power-on and System Reset. The factory preprogrammed MAC address is permanent and will be restored to the MAC registers after each Reset ...
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... Transmit logic is held in Reset. TXRTS (ECON1<1>) is automatically cleared by hardware when this bit is set Transmit logic is not in Reset (normal operation) Note 1: Reset value on POR events only. All other Resets leave these bits unchanged. 2010 Microchip Technology Inc. ENC424J600/624J600 (1) (1) R/W-0 R/W-1 R/W-0 ...
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... ENC424J600/624J600 REGISTER 8-1: ECON2: ETHERNET CONTROL REGISTER 2 (CONTINUED) bit 6 RXRST: Receive Logic Reset bit 1 = Receive logic is held in Reset. RXEN (ECON1<0>) is automatically cleared by hardware when this bit is set Receive logic is not in Reset (normal operation) bit 4 ETHRST: Master Ethernet Reset bit 1 = All TX, RX, MAC, PHY, DMA, modular exponentiation, hashing and AES logic, and registers (excluding COCON) are reset. Hardware self-clears this bit to ‘ ...
Page 81
... These configurations require that a bi-color LED be connected between the LEDA and LEDB pins, and that LACFG<3:0> and LBCFG<3:0> be set to the same value. See Section 2.5.1 “Using Bi-Color LEDs” for detailed information. 2010 Microchip Technology Inc. ENC424J600/624J600 R/W-0 R/W-0 R/W-1 ...
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... ENC424J600/624J600 REGISTER 8-3: MACON2: MAC CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — DEFER BPEN bit 15 R/W-1 R/W-0 R/W-1 PADCFG2 PADCFG1 PADCFG0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘ 0 ’ bit 14 DEFER: Defer Transmission Enable bit (applies to half duplex only When the medium is occupied, the MAC will wait indefinitely for it to become free when attempting to transmit (use this setting for IEEE 802 ...
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... The register value should be programmed to the desired period in nibble times minus 6. The recommended setting is 12h which represents the minimum IEEE specified Inter-Packet Gap (IPG) of 0.96 s (at 100 Mb/s) or 9.6 s (at 10 Mb/s). 2010 Microchip Technology Inc. ENC424J600/624J600 U-0 U-0 U-0 — ...
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... ENC424J600/624J600 REGISTER 8-5: MAIPG: MAC INTER-PACKET GAP REGISTER U-0 R/W-0 R/W-0 — bit 15 U-0 R/W-0 R/W-0 — IPG6 IPG5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘ 0 ’ bit 14-8 Reserved: Write as ‘ 0001100 ’ (0Ch) bit 7 Unimplemented: Read as ‘ ...
Page 85
... TRANSMITTING AND RECEIVING PACKETS Beyond providing the transceiver interface to the network medium, ENC424J600/624J600 devices also handle many of the mechanical tasks of packet management, off-loading much of the routine Ethernet housekeeping from the host application. The device manages the separate transmit and receive buffers, ...
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... ENC424J600/624J600 FIGURE 9-2: EXAMPLES FOR SELECTING ETXLEN VALUES Example 1: Source Address and Padding Provided by Application 0120h Destination Source Address Address ETXST = 0120h ETXLEN = 3Ch Example 2: Padding Provided by Application, Source Address to be Inserted by ENCX24J600 0120h Destination Protocol Address ETXST = 0120h ETXLEN = 36h ...
Page 87
... TXRTS bit to prevent a single packet from stalling device operation. When 2010 Microchip Technology Inc. ENC424J600/624J600 any of these flags are set, the packet was not success- fully transmitted and the host controller should determine whether to retry or ignore the error. ...
Page 88
... ENC424J600/624J600 In full duplex, the MAC inhibits transmission of any packets until the pause timer expires when two conditions are met: • Flow control is enabled (RXPAUS bit is set) and • A valid pause frame was received from the remote node It will still be possible for software to set the TXRTS bit to start a transmission ...
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... Packet Alternatively, poll the PKTCNT bits for a non-zero value. 2010 Microchip Technology Inc. ENC424J600/624J600 9.2.2 STORAGE OF INCOMING PACKETS Packets are stored sequentially in the receive buffer. Each frame is stored as it was presented to the MAC, including all padding and frame check (CRC) bytes, but excluding any preamble or start of stream/frame delim- iter bytes ...
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... ENC424J600/624J600 FIGURE 9-4: EXAMPLE OF A RECEIVED PACKET IN BUFFER MEMORY Byte Address : Previous : Packet 011Dh 011Fh 0121h 0123h 0125h 0127h 0129h 012Bh 012Dh 012Fh 0131h Current Packet 0133h 0135h 0137h : : 015Fh 0161h 0163h 0165h 0167h 0169h Next 016Bh Packet 016Dh 016Fh : : DS39935C-page 88 ...
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... Packet Previously Ignored 1 15:0 Received Byte Count 0 2010 Microchip Technology Inc. ENC424J600/624J600 Description 00h ‘ 0 ’ Current frame met criteria for the Unicast Receive filter. Current frame met criteria for the Pattern Match Receive filter as configured when the packet was received. ...
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... ENC424J600/624J600 REGISTER 9-1: ECON1: ETHERNET CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 MODEXST HASHEN HASHOP bit 15 R/W-0 R/W-0 R/W-0 FCOP1 FCOP0 DMAST bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 MODEXST: Modular Exponentiation Start bit 1 = Modular exponentiation calculation started/busy; automatically cleared by hardware when done ...
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... TXRTS: Transmit Request to Send Status/Control bit 1 = Transmit an Ethernet frame; automatically cleared by hardware when done 0 = Transmit logic done/Idle bit 0 RXEN: Receive Enable bit 1 = Packets which pass the current RX filter configuration are written to the receive buffer 0 = All packets received are ignored 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 91 ...
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... ENC424J600/624J600 REGISTER 9-2: ETXSTAT: ETHERNET TRANSMIT STATUS REGISTER U-0 U-0 U-0 — — — bit 15 R-0 R-0 R-0 (1) DEFER r r bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘ 0 ’ bit 12-11 Reserved: Ignore on read ...
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... No Ethernet link present bit 7-0 PKTCNT<7:0>: Receive Packet Count bits Number of complete packets that are saved in the RX buffer and ready for software processing. Set the PKTDEC (ECON1<8>) bit to decrement this field. 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R-0 R-0 CLKRDY r ...
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... ENC424J600/624J600 NOTES: DS39935C-page 94 2010 Microchip Technology Inc. ...
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... RECEIVE FILTERS To minimize the number of frames that the host controller must process, ENC424J600/624J600 devices incorpo- rate 11 different receive filters to discard unwanted frames. The following filters are available: • CRC Error Collection Filter • Runt Error Collection Filter • CRC Error Rejection Filter • ...
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... ENC424J600/624J600 REGISTER 10-1: ERXFCON: ETHERNET RX FILTER CONTROL REGISTER R/W-0 R/W-0 U-0 HTEN MPEN — bit 15 R/W-0 R/W-1 R/W-0 CRCEEN CRCEN RUNTEEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 HTEN: Hash Table Collection Filter Enable bit ...
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... This filtering decision can be overridden by the CRC Error Rejection filter and Runt Error Rejection filter decisions, if enabled, by CRCEN or RUNTEN. 2: This filtering decision can be overridden by the CRC Error Collection filter and Runt Error Collection filter decisions, if enabled, by CRCEEN or RUNTEEN. 2010 Microchip Technology Inc. ENC424J600/624J600 (2) (2) (1) (1) (1) ...
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... ENC424J600/624J600 FIGURE 10-1: RECEIVE FILTER DECISION TREE Packet Arrives No CRC is valid? Yes Yes Length < 64 bytes? No Discard Packet Note 1: For details on the Pattern Match filter, refer to Section 10.11 “Pattern Match Collection Filter” . DS39935C-page 98 Yes CRCEEN set? No Yes RUNTEEN set? No Yes ...
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... Microchip Technology Inc. ENC424J600/624J600 This filter is enabled at power-up. To disable this filter, clear CRCEN (ERXFCON<6>). If the filter is disabled, all frames will be passed on to the next lower priority filter, regardless of CRC validity ...
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... ENC424J600/624J600 10.7 Multicast Collection Filter The Multicast Collection filter checks the destination address of incoming frames. If the Least Significant bit (LSb) of the first byte of the destination address is set, the frame will be accepted. This represents all Multicast frames. If the frame has a Unicast destination, it will be passed on to the next filter ...
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... 2010 Microchip Technology Inc. ENC424J600/624J600 Packet. This pattern may be located anywhere within the packet. Other fields in the packet, such as the destination address or bytes preceding or following the Magic Packet pattern, are ignored. This filter is disabled at power-up. To enable this filter, set MPEN (ERXFCON<14>). If the filter is disabled or the received packet is not a Magic Packet, the frame will be passed to the next lower priority filter ...
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... ENC424J600/624J600 10.11 Pattern Match Collection Filter The Pattern Match filter accepts frames that match or do not match a specific pattern. This filter is useful for accepting frames that contain sequences. Pattern matching is accomplished by choosing a 64-byte window within the first 128 bytes of a frame, then selecting some or all of those bytes for a checksum calculation ...
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... Bytes used for Checksum Computation Values used for Checksum Computation = {88h, AAh, 09h, 0Ah, 0Bh, 0Ch, 0Dh, 00h} (00h padding byte added by hardware) Note: Received data is shown in hexadecimal. Byte numbers are shown in decimal format. 2010 Microchip Technology Inc. ENC424J600/624J600 SA Type/Length ...
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... ENC424J600/624J600 NOTES: DS39935C-page 104 2010 Microchip Technology Inc. ...
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... This feature is commonly used to prevent buffer overruns while receiving data. ENC424J600/624J600 devices are capable of both automatic and manual flow control. The hardware can advertise when it is temporarily unable to receive data and delay transmissions when a remote system does the same ...
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... ENC424J600/624J600 11.2 Manual and Automatic Flow Control Note: When flow control is used in conjunction with auto-negotiation, also set the ADPAUS bits (PHANA<11:10>) to ‘ 01 ’ during initial- ization. See Section 12.0 “Speed/Duplex Configuration and Auto-Negotiation” for more information. 11.2.1 MANUAL FLOW CONTROL Manual flow control is enabled by default on device power-up and whenever the AUTOFC bit (ECON2< ...
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... PASSALL: Pass All Received Frames Enable bit 1 = Control frames received by the MAC are written into the receive buffer if not filtered out 0 = Control frames are discarded after being processed by the MAC (normal operation) bit 0 Reserved: Write as ‘ 1 ’ 2010 Microchip Technology Inc. ENC424J600/624J600 U-0 R/W-0 R/W-0 — r ...
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... ENC424J600/624J600 NOTES: DS39935C-page 108 2010 Microchip Technology Inc. ...
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... SPEED/DUPLEX CONFIGURATION AND AUTO-NEGOTIATION ENC424J600/624J600 devices are capable of operation at 10Base-T and 100Base-TX speeds in Half-Duplex and Full-Duplex modes for each. The speed and Duplex mode can be selected manually, or the part can be configured to automatically select the optimum link parameters based on the capabilities of the link partner. ...
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... ENC424J600/624J600 When LINKIF link status change interrupt flag is set, it means auto-negotiation or parallel detection is complete. Once auto-negotiation is complete, the MAC registers related to Duplex mode must be reconfigured. Determine the new Duplex mode by reading the PHYDPX bit (ESTAT<10>). Once this is done, update REGISTER 12-1: ...
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... Reserved: Ignore on read bit 0 EXTREGS: Extended Capabilities Registers Present Status bit 1 = PHY has extended capability registers at addresses, 16 thru 31 Note 1: This is the only valid state for this bit; a ‘ 0 ’ represents an invalid condition. 2010 Microchip Technology Inc. ENC424J600/624J600 (1) (1) R-1 R-1 R-0 FULL10 ...
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... ENC424J600/624J600 REGISTER 12-3: PHSTAT2: PHY STATUS REGISTER 2 R/W-x R/W-x R/W bit 15 R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Reserved: Write as ‘ 0 ’, ignore on read bit 4 PLRITY: TPIN+/- Polarity Status bit (applies to 10Base-T only Wiring on the TPIN+/- pins is reversed polarity ...
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... Local PHY is incapable of 10Base-T half-duplex operation bit 4-0 ADIEEE<4:0>: Advertise IEEE Standard Selector Field bits 00001 = IEEE 802.3 Std. All other values reserved by IEEE. Always specify a selector value of ‘ 00001 ’ for this device. 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R/W-0 R/W-0 r ADPAUS1 ...
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... ENC424J600/624J600 REGISTER 12-6: PHANLPA: PHY AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER R-0 R-0 R-0 LPNP LPACK LPFAULT bit 15 R-0 R-0 R-0 LP100 LP10FD LP10 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 LPNP: Link Partner Next Page Ability bit ...
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... PHANLPA register has been written with a new value from the link partner; automatically cleared when register is read 0 = PHANLPA contents have not changed since the last read of PHANE bit 0 LPANABL: Link Partner Auto-Negotiation Able Status bit 1 = Link partner implements auto-negotiation 0 = Link partner does not implement auto-negotiation 2010 Microchip Technology Inc. ENC424J600/624J600 R-0 R-0 R R/LH-0 ...
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... ENC424J600/624J600 NOTES: DS39935C-page 116 2010 Microchip Technology Inc. ...
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... INTERRUPTS ENC424J600/624J600 devices have multiple interrupt sources tied to a single output pin, allowing the device to signal the occurrence of events to the host controller. The interrupt pin is active-low and is designed for use by host controllers that can detect falling edges. Interrupts can also be used on a polling basis without connecting the interrupt pin. To use interrupts in this manner, monitor the INT bit (ESTAT< ...
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... ENC424J600/624J600 REGISTER 13-1: EIR: ETHERNET INTERRUPT FLAG REGISTER R/W-0 R/W-0 R/W-0 CRYPTEN MODEXIF HASHIF bit 15 R/W-0 R-0 R/W-0 r PKTIF DMAIF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 CRYPTEN: Modular Exponentiation and AES Cryptographic Modules Enable bit 1 = All cryptographic engine modules are enabled 0 = Modular exponentiation and AES modules are disabled and powered down ...
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... PKTCNT field is saturated at FFh interrupt pending bit 0 PCFULIF: Packet Counter Full Interrupt Flag bit 1 = PKTCNT field has reached FFh. Software must decrement the packet counter to prevent the next RX packet from being dropped interrupt pending 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 119 ...
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... ENC424J600/624J600 REGISTER 13-2: EIE: ETHERNET INTERRUPT ENABLE REGISTER R/W-1 R/W-0 R/W-0 INTIE MODEXIE HASHIE bit 15 R/W-0 R/W-0 R/W-0 r PKTIE DMAIE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 INTIE: INT Global Interrupt Enable bit 1 = INT pin is controlled by the INT status bit (ESTAT<15>) ...
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... Interrupt Sources ENC424J600/624J600 devices have multiple interrupt sources, each individually selectable. The various interrupt sources are described in the following sections. For any of the following interrupts to propagate out of the device, the INTIE (EIE<15>) global interrupt enable must be set. 13.1.1 MODULAR EXPONENTIATION ...
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... The host controller and other subsystems can be placed in Low-Power mode, then configured to wake-up when a Magic Packet™ is received by the ENC424J600/624J600 devices. For Wake-on-LAN to operate correctly, the device must not be in Low-Power mode and the receive module must be enabled. When a Magic Packet arrives, the device wakes the host controller via the INT signal ...
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... DIRECT MEMORY ACCESS (DMA) CONTROLLER ENC424J600/624J600 devices incorporate a Direct Memory Access (DMA) controller to reduce the burden on the host processor. The module serves the following purposes: • Copying data from one part of the packet buffer to another. • Copying data between the packet buffer and one of the memory mapped cryptographic engines. • ...
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... ENC424J600/624J600 Copy operations are performed starting with the first byte or word at the source address and incrementing forward legal to use the DMA to move a block of data backwards in memory, even if the source and destination memory ranges overlap. For example 65-byte packet of data was located starting at memory ...
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... CRYPTOGRAPHIC SECURITY ENGINES To reduce the processing requirements of the host controller, ENC424J600/624J600 devices incorporate three different cryptographic security engines. These security engines perform the types of encryptions, decryptions and mathematical computations that are most commonly used for network security functions. They accelerate the computation of public/private key pair negotiations, message hash authentication and bulk data encryption ...
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... ENC424J600/624J600 To perform a modular exponentiation: 1. Copy the values for and M into the 24-Kbyte SRAM. 2. Set CRYPTEN (EIR<15>) to turn on the Modular Exponentiation module. 3. Use the DMA to transfer E to addresses, 7800h through 783Fh (512-bit), 785F (768-bit) or 787Fh (1024-bit). If the value is shorter than the chosen operand length, left-pad the value with zeros ...
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... To allow for hashes to be computed over any length of data, the integral length of 4 restriction does not apply to the last transfer (when HASHLST is set). 2010 Microchip Technology Inc. ENC424J600/624J600 15.2.1 MD5 HASHING The module implements the MD5 function, as described in the Internet Engineering Task Force RFC 1321, “ ...
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... ENC424J600/624J600 15.2.2 SHA-1 HASHING The module implements the SHA-1 function as described in the NIST Federal Information Processing Standard (FIPS) Publication 180-1 . The resulting digest is 160 bits (20 bytes) in length. To calculate a SHA-1 digest: 1. Set SHA1MD5 (ECON2<12>). Clear HASHOP and HASHLST (ECON1<13:12>). 2. Set HASHEN (ECON1<14>). ...
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... Microchip Technology Inc. ENC424J600/624J600 15.2.4 MD5/SHA-1 HASH PERFORMANCE The implications noted in Section 15.2.1 “MD5 Hash- ing” and Section 15.2.2 “SHA-1 Hashing” are that the hashing engine is extremely fast and net through- put is primarily limited by the DMA ...
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... ENC424J600/624J600 To initialize decryption using a known encryption key: 1. Verify that AESST is clear, indicating that the engine is Idle. 2. Configure AESLEN<1:0> to select the correct key size. 3. Use the DMA to transfer the encryption key to address 7C00h. Keys shorter than 256 bits should be left-aligned. 4. Configure AESOP<1:0> (ECON1<10:9>) to ‘ ...
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... IV Key DATA KEY ENCRYPTER Ciphertext 0 2010 Microchip Technology Inc. ENC424J600/624J600 5. Wait for the hardware to clear AESST. 6. Read the plaintext message from TEXTA at 7C20h. 7. Repeat steps 3 through 6 for subsequent blocks. The context for ECB mode includes only the encryption key. No additional context data needs to be saved. ...
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... ENC424J600/624J600 To encrypt a block using CBC mode: 1. Load the encryption key as described in Section 15.3.1 “Key Support” Set AESOP<1:0> (ECON1<10:9>) to ‘ 01 ’. 3. Copy the Initialization Value (IV) to TEXTA at 7C20h. 4. Copy the plaintext message to TEXTB at 7C30h. 5. Set AESST (ECON1<11>) to initiate the encryption. 6. Wait for the hardware to clear AESST. ...
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... Key DATA KEY DATA ENCRYPTER ENCRYPTER Plaintext Plaintext 0 Ciphertext 0 2010 Microchip Technology Inc. ENC424J600/624J600 3. Copy the Initialization Value (IV) to TEXTA at 7C20h. 4. Set AESST to initiate the encryption. 5. Copy the ciphertext message to TEXTB at 7C30h. 6. Wait for the hardware to clear AESST. 7. Read the plaintext message from XOROUT at 7C40h ...
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... ENC424J600/624J600 To encrypt a block using OFB mode: 1. Load the encryption key as described in Section 15.3.1 “Key Support” Set AESOP<1:0> (ECON1<10:9>) to ‘ 00 ’. 3. Copy the Initialization Value (IV) to TEXTA at 7C20h. 4. Set AESST (ECON1<11>) to initiate the encryption. 5. Copy the plaintext message to TEXTB at 7C30h. 6. Wait for the hardware to clear AESST. ...
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... Read the ciphertext message from XOROUT at 7C40h. 8. Repeat steps 3 through 7 for subsequent blocks. 2010 Microchip Technology Inc. ENC424J600/624J600 To decrypt a block using CTR mode: 1. Load the encryption key as described in Section 15.3.1 “Key Support” . Note that this mode does not make use of a decryption key. ...
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... ENC424J600/624J600 NOTES: DS39935C-page 136 2010 Microchip Technology Inc. ...
Page 139
... Link Change Interrupt Flag, LINKIF (EIR<11>), and PHYLNK status bit (ESTAT<8>). 16.2 Energy Detect Power-Down ENC424J600/624J600 devices also support an Energy Detect Power-Down mode. In this mode, the PHY remains powered down until a signal is detected on the Ethernet interface. While no packets can be sent or received, the internal PHY configuration is maintained ...
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... ENC424J600/624J600 A device in Energy Detect Power-Down mode does not transmit link pulses, but passively listens for the remote link partner to transmit a signal in order to wake the device. If the remote device is also in a similar Passive Listening mode, neither device will wake-up. This should not cause problems for normal Ethernet ...
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... Energy detect circuit has detected energy on the TPIN+/- pins within the last 256 energy has been detected on the TPIN+/- pins within the last 256 ms bit 0 Reserved: Write as ‘ 0 ’, ignore on read Note 1: Intended for testing purposes only. Do not use in 10 Mbps operation. 2010 Microchip Technology Inc. ENC424J600/624J600 R/W-0 R/W-0 R/W-0 r EDTHRES r ...
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... ENC424J600/624J600 NOTES: DS39935C-page 140 2010 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. 2010 Microchip Technology Inc. ENC424J600/624J600 and V , with respect to V ................................................. -0.3V to 4.0V ...
Page 144
... ENC424J600/624J600 17.1 DC Characteristics: ENC424J600/624J600 TABLE 17-1: THERMAL OPERATING CONDITIONS Rating ENC424J600/624J600: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: – INT I/O Pin Power Dissipation: = ({ – -)/ TPOUT TXCT Maximum Allowed Power Dissipation ...
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... TABLE 17-3: DC CHARACTERISTICS: ENC424J600/624J600 (INDUSTRIAL) DC CHARACTERISTICS Param. Sym Characteristic No. D001 V Supply Voltage DD D002 V Start Voltage to Ensure Internal V POR DD Power-on Reset Signal D003 S V Rise Rate to Ensure Internal VDD DD Power-on Reset Signal V Input High Voltage IH D004 Digital Input Pins D005 OSC1 Pin ...
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... ENC424J600/624J600 TABLE 17-3: DC CHARACTERISTICS: ENC424J600/624J600 (INDUSTRIAL) (CONTINUED) DC CHARACTERISTICS Param. Sym Characteristic No. I Power-Down Current PD Energy Detect Power-Down Sleep V Peak Differential Output Voltage TPOUT 100Base-TX 10Base-T V 10Base-T RX Differential Squelch SQ Threshold Note 1: Excludes TX transformer center tap and LEDA/LEDB currents; cryptographic engine module disabled (EIR< ...
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... AC Characteristics: ENC424J600/624J600 (Industrial) AC CHARACTERISTICS TABLE 17-6: OSCILLATOR TIMING CHARACTERISTICS Param. Sym Characteristic No. F Clock In Frequency OSC T Clock In Period OSC T Duty Cycle DUTY (external clock input) f Clock Frequency Error TABLE 17-7: CLKOUT PIN TIMING SPECIFICATIONS Param. Sym Characteristic No. F CLKOUT Frequency ...
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... ENC424J600/624J600 FIGURE 17-1: SPI INPUT TIMING 1/F SCK CS T CSS SCK MSb In SO FIGURE 17-2: SPI OUTPUT TIMING CS 1/F SCK SCK MSb Out SI LSb In TABLE 17-9: SPI INTERFACE AC CHARACTERISTICS Sym Characteristic F SPI Clock Frequency SCK T SCK Duty Cycle DUTY T CS Setup Time ...
Page 149
... WR, WRL, WRH, EN, BxSEL PSP Deassertion Time T 12 CS, Address Setup Time PSP Assertion Time PSP T 14 Address Hold Time PSP Deassertion Time PSP 2010 Microchip Technology Inc. ENC424J600/624J600 Min Typ Max Units 1 — — ns — — — 4.5 — — ns 3.5 — ...
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... ENC424J600/624J600 NOTES: DS39935C-page 148 2010 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2010 Microchip Technology Inc. ENC424J600/624J600 Example ENC424J600 -I/ 1010017 Example ENC424J600 -I/ 1010017 Example ENC624J600 -I/ 1010017 e ...
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... ENC424J600/624J600 18.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± %RG\ >4)1@ 1RWH 1RWHV DS39935C-page 150 2010 Microchip Technology Inc. ...
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... PP %RG\ >4)1@ 1RWH 2010 Microchip Technology Inc. ENC424J600/624J600 DS39935C-page 151 ...
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... ENC424J600/624J600 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH β 1RWHV DS39935C-page 152 [ [ PP %RG\ PP >74)3@ α φ 2010 Microchip Technology Inc. ...
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... Microchip Technology Inc. ENC424J600/624J600 [ [ PP %RG\ PP >74)3@ DS39935C-page 153 ...
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... ENC424J600/624J600 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH β 1RWHV DS39935C-page 154 [ [ PP %RG\ PP >74)3@ φ 2010 Microchip Technology Inc. α ...
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... Microchip Technology Inc. ENC424J600/624J600 [ [ PP %RG\ PP >74)3@ DS39935C-page 155 ...
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... ENC424J600/624J600 NOTES: DS39935C-page 156 2010 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision A (March 2009) Original data sheet for ENC424J600/624J600 devices. Revision B (July 2009) Removed preliminary from the data sheet. Section 1.0 “Device Overview” and Section 7.0 “Reset” had minor edits. Revision C (January 2010) Section 5.3.3 “MODE 3” and Section 5.3.4 “MODE 4” ...
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... ENC424J600/624J600 NOTES: DS39935C-page 158 2010 Microchip Technology Inc. ...
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... Copying Memory ...................................................... 123 Performance ............................................................. 124 E E Registers ......................................................................... 19 Electrical Characteristics .................................................. 141 Absolute Maximum Ratings ...................................... 141 ENC424J600/624J600 Register File Summary ............ 26–27 Energy Detect Power-Down ............................................. 137 Equations Increment Logic for EGPRDPT and EGPWRPT ........ 35 Increment Logic for ERXRDPT and ERXWRPT......... 36 Increment Logic for EUDARDPT and EUDAWRPT ................................................ 36 Errata ...
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... ENC424J600/624J600 G General Power-Down Sequence....................................... 137 H Host Interface Pins........................................................ 13–15 I I/O Level Shifting................................................................. 15 Initialization After Link Establishment ............................................. 76 CLKOUT Frequency ................................................... 75 MAC ............................................................................ 75 PHY............................................................................. 76 Receive Buffer ............................................................ 75 Receive Filters ............................................................ 75 Reset........................................................................... 75 Transmit Buffer ........................................................... 75 INT Pin ................................................................................ 13 Internet Address................................................................ 162 Interrupts Sources ............................................................. 121–122 Wake-on-LAN/Remote Wake-up .............................. 122 INTIE Global Interrupt Enable Bit........................................ 117 M MAC Registers ...
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... Banked SFR ....................................................... 45 SRAM Buffer ....................................................... 49 Unbanked SFR ................................................... 47 Single Byte Instructions .............................................. 41 Summary Table........................................................... 40 Three-Byte Instructions............................................... 43 Two-Byte Instructions ................................................. 42 2010 Microchip Technology Inc. ENC424J600/624J600 SRAM Buffer....................................................................... 32 Buffer Pointers............................................................ 34 Circular Wrapping ERXDATA Pointer .............................................. 36 EUDADATA Pointer...................................... 36–37 Circular Wrapping with EGPDATA Pointer ................. 35 Direct Access.............................................................. 33 General Purpose Buffer.............................................. 33 Indirect Access ...
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... ENC424J600/624J600 NOTES: DS39935C-page 162 2010 Microchip Technology Inc. ...
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... To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. 2010 Microchip Technology Inc. ENC424J600/624J600 CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: ENC424J600/624J600 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... TQFP (Thin Quad Flatpack) Pattern Three-Digit Code or Special Requirements (blank otherwise Engineering Sample 2010 Microchip Technology Inc. ENC424J600/624J600 XXX Examples: Pattern a) ENC424J600-I/ML = Industrial temp., QFN package. b) ENC424J600-I/PT = Industrial temp., 44 leads TQFP package. c) ENC624J600T-I/PT = Industrial temp., 64 leads TQFP package, tape and reel. (1) ; ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...