SC18IS602BIPW,112 NXP Semiconductors, SC18IS602BIPW,112 Datasheet

IC BRIDGE SPI/I2C 16-TSSOP

SC18IS602BIPW,112

Manufacturer Part Number
SC18IS602BIPW,112
Description
IC BRIDGE SPI/I2C 16-TSSOP
Manufacturer
NXP Semiconductors
Datasheets

Specifications of SC18IS602BIPW,112

Controller Type
I²C Bus Controller
Interface
I²C
Voltage - Supply
2.4 V ~ 3.6 V
Current - Supply
11mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Operating Temperature Classification
Military
Operating Temperature (max)
125C
Package Type
TSSOP
Rad Hardened
No
Maximum Operating Frequency
4.5 MHz
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.4 V
For Use With
568-4705 - DEMO BOARD I2C TO SPI SC18IS602
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-4785-5
935286182112
SC18IS602BIPW
SC18IS602BIPW,112
SC18IS602BIPW

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Part Number:
SC18IS602BIPW,112
Manufacturer:
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Quantity:
463
1. General description
2. Features
3. Applications
The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a
standard I
communicate directly with SPI devices through its I
operates as an I
SC18IS602/602B/603 controls all the SPI bus-specific sequences, protocol, and timing.
The SC18IS602/602B has its own internal oscillator, while the SC18IS603 requires an
external clock source for operation. SC18IS602 and SC18IS603 do not support SS2
function as SPI slave select signal; this pin can only be used as GPIO2.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SC18IS602/602B/603
I
Rev. 04 — 11 March 2008
I
SPI master operating up to 1.8 Mbit/s (SC18IS602/602B) or 4 Mbit/s (SC18IS603)
200-byte data buffer
Up to four slave select outputs
Up to four programmable I/O pins
Operating supply voltage: 2.4 V to 3.6 V
Low power mode
Internal oscillator option
Active LOW interrupt output
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 that exceeds 100 mA
Very small 16-pin TSSOP
Converting I
Adding additional SPI bus controllers to an existing system
2
2
C-bus slave interface operating up to 400 kHz
C-bus to SPI bridge
2
C-bus of a microcontroller and an SPI bus. This allows the microcontroller to
2
2
C-bus to SPI
C-bus slave-transmitter or slave-receiver and an SPI master. The
2
C-bus. The SC18IS602/602B/603
Product data sheet

Related parts for SC18IS602BIPW,112

SC18IS602BIPW,112 Summary of contents

Page 1

SC18IS602/602B/603 2 I C-bus to SPI bridge Rev. 04 — 11 March 2008 1. General description The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a standard I communicate directly with SPI devices through its I operates ...

Page 2

... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name SC18IS602IPW TSSOP16 SC18IS602BIPW TSSOP16 SC18IS603IPW TSSOP16 5. Block diagram SCL SDA RESET INT (1) Unused slave select outputs may be used for GPIO. Fig 1. SCL SDA RESET INT (1) Unused slave select outputs may be used for GPIO; SC18IS603 does not have SS3. ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 1 SS0/GPIO0 SS1/GPIO1 2 RESET SC18IS602IPW SS SC18IS602BIPW 5 MISO MOSI 6 SDA 7 8 SCL a. SC18IS602/602B Fig 3. Pin configuration for TSSOP16 6.2 Pin description Table 2. Pin description Symbol Pin SC18IS602, SC18IS603 SC18IS602B SS0/GPIO0 1 1 SS1/GPIO1 2 2 RESET MISO 5 5 MOSI ...

Page 4

... C-bus SC18IS602/602B/603 2 I C-bus configuration Rev. 04 — 11 March 2008 SC18IS602/602B/603 2 I C-bus to SPI bridge 2 C-bus and an SPI interface. It Figure 4. (Refer to NXP Semiconductors’ SDA SCL C-BUS I C-BUS DEVICE DEVICE 002aac445 2 C-bus interface that supports 2 C-bus master is reading data from SC18IS60x, © ...

Page 5

... NXP Semiconductors 7.1.1 Addressing Fig 5. The first seven bits of the first byte sent after a START condition defines the slave address of the device being accessed on the bus. The eighth bit determines the direction of the message. A ‘0’ in the least significant position of the first byte means that the master will write information to a selected slave. A ‘ ...

Page 6

... NXP Semiconductors the Function ID. There is no restriction on the number or combination of Slave Selects that can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the user should be aware of possible contention on the data outputs of the SPI slave devices. Table [1] SS3 does not exist in the SC18IS603. ...

Page 7

... NXP Semiconductors 7.1.5 Configure SPI Interface - Function ID F0h The SPI hardware operating mode, data direction, and frequency can be changed by sending a ‘Configure SPI Interface’ command to the I Fig 10. Configure SPI Interface After the SC18IS602/602B/603 address is transmitted on the bus, the Configure SPI Interface Function ID (F0h) is sent followed by a byte which will defi ...

Page 8

... NXP Semiconductors 7.1.6 Clear Interrupt - Function ID F1h An interrupt is generated by the SC18IS602/602B/603 after any SPI transmission has been completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’ command not necessary to clear the interrupt; when polling the device, this function may be ignored. ...

Page 9

... NXP Semiconductors 7.1.9 GPIO Read - Function ID F5h The state of the pins defined as GPIO may be read into the SC18IS602/602B/603 data buffer using the GPIO Read function. Fig 14. GPIO Read Note that this function does not return the value of the GPIO. To receive the GPIO contents, a one-byte Read Buffer command would be required ...

Page 10

... NXP Semiconductors 7.1.11 GPIO Configuration - Function ID F7h The pins defined as GPIO may be configured by software to one of four types on a pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only. Two bits select the output type for each port pin. Table 9. 7 SS3.1 [1] SS3 ...

Page 11

... NXP Semiconductors A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on ...

Page 12

... NXP Semiconductors Fig 17. Open-drain output configuration 7.1.11.3 Input-only configuration The input-only pin configuration is shown in also has a glitch suppression circuit. Fig 18. Input-only configuration 7.1.11.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes but provides a continuous strong pull-up when the port latch contains a logic 1 ...

Page 13

... NXP Semiconductors 7.2 External clock input (SC18IS603) In this device, the processor clock is derived from an external source driving the CLKIN pin. The rate may be from MHz. Using the external clock allows higher frequencies from the SPI interface, thus the SPI Master operating can Mbit/s. The CLKIN frequency does not affect the ...

Page 14

... NXP Semiconductors C-bus to SPI communications example The following example describes a typical sequence of events required to read the contents of an SPI-based EEPROM. This example assumes that the SC18IS602/602B/603 is configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP condition is ‘SP’. The data is presented in hexadecimal format. 1. The fi ...

Page 15

... NXP Semiconductors You can see that on the I SPI bus. The first byte is the SC18IS60x address, followed by three dummy data bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM before it actually places data on the bus (command 03h, subaddress 0030h). ...

Page 16

... NXP Semiconductors 10. Static characteristics Table 12. Static characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) V HIGH-LOW threshold voltage th(HL) V LOW-HIGH threshold voltage th(LH) V hysteresis voltage hys V LOW-level output voltage OL V HIGH-level output voltage ...

Page 17

... NXP Semiconductors 11. Dynamic characteristics Table 13. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency External clock input f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...

Page 18

... NXP Semiconductors SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 20. SPI master timing (CPHA = 0) SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 21. SPI master timing (CPHA = 0.45 V Fig 22. External clock timing SC18IS602_602B_603_4 ...

Page 19

... NXP Semiconductors 12. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 21

... NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 22

... NXP Semiconductors Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Abbreviations Table 16. Acronym CDM CPU EEPROM ESD GPIO HBM I C-bus LSB MM MSB SPI SC18IS602_602B_603_4 ...

Page 23

... NXP Semiconductors 15. Revision history Table 17. Revision history Document ID Release date SC18IS602_602B_603_4 20080311 • Modifications: added Type number SC18IS602BIPW • Section 1 “General • Section 6 “Pinning – added “SC18IS602BIPW” to – • Table 3 “Function ID 01h to • Section 7.1 “I SC18IS602_603_3 20070813 SC18IS602_603_2 ...

Page 24

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 25

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 2 7.1 I C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 4 7.1.1 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 Write to data buffer . . . . . . . . . . . . . . . . . . . . . . 5 7.1.3 SPI read and write - Function ID 01h to 0Fh . . 5 7 ...

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