CY7C63310-PXC Cypress Semiconductor Corp, CY7C63310-PXC Datasheet
CY7C63310-PXC
Specifications of CY7C63310-PXC
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CY7C63310-PXC Summary of contents
Page 1
... Available in 16 and 18-pin PDIP; 16, 18, and 24-pin SOIC; ■ 24-pin QSOP, and 32-pin QFN packages Industry standard programmer support ■ 0.1 Applications The CY7C63310/CY7C638xx is targeted for the following applications: PC HID devices ■ Mice (optomechanical, optical, trackball) ❐ Gaming ■ ...
Page 2
... Low Voltage Detect Control .......................................... 32 General Purpose I/O (GPIO) Ports ................................ 34 Serial Peripheral Interface (SPI) .................................... 41 Timer Registers .............................................................. 44 Interrupt Controller ......................................................... 51 Regulator Output ............................................................ 57 Document 38-08035 Rev. *N CY7C63310, CY7C638xx USB/PS2 Transceiver ..................................................... 58 USB Transceiver Configuration .................................... 58 USB Serial Interface Engine (SIE) ................................. 58 USB Device ..................................................................... 59 USB Mode Tables ........................................................... 62 Register Summary .......................................................... 65 Voltage Vs CPU Frequency Characteristics ...
Page 3
... External Clock POR / Low-Voltage Detect Document 38-08035 Rev Low-Speed Interrupt 4 3VIO/SPI Extended USB SIE Control Pins IO Pins RAM Flash M8C CPU Up to 256 Byte Byte Watchdog Timer CY7C63310, CY7C638xx Wakeup GPIO Timer pins 16-bit Free 12-bit Timer running timer Page [+] Feedback ...
Page 4
... D– pins as the serial programming mode interface. The programming protocol is not USB. 4. Conventions In this data sheet, bit positions in the registers are shaded to indicate which members of the enCoRe II family implement the bits. Available in all enCoRe II family members CY7C638(1/2/3)3 only drops below a CC CY7C63310, CY7C638xx Page [+] Feedback ...
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... CY7C63833 32-Pin Sawn QFN 32-Pin QFN P0.6/TIO1 1 P1.5/SMOSI 24 P0.5/TIO0 2 P1.4/SCLK 23 P0.4/INT2 3 P3.1 22 P0.3/INT1 4 P3.0 21 P0.2/INT0 5 P1.3/SSEL 20 P0 P0.0 7 P1.2/VREG 18 P2 CY7C63310, CY7C638xx CY7C63803 16-Pin SOIC TIO1/P0.6 16 P1.6/SMISO 1 15 TIO0/P0.5 2 P1.5/SMOSI P1.4/SCLK INT2/P0 INT1/P0.3 13 P1.3/SSEL 4 12 P1.2/VREG INT0/P0 P0 P1.1/D– P0 P1.0/ P1 P1.6/SMISO P1.5/SMOSI 3 ...
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... CY7C63310, CY7C638xx Legend 13 Die step = 1792.98 μm x 2272.998 μm Die size = 1727 μm x 2187 μm Bond pad opening = 70 μ μm 12 Die thickness = 14 mils Page ...
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... CY7C63310, 3.3 V I/O is still available P1.6/SMISO GPIO Port 1 bit 6. Configured individually. Alternate function is SMISO signal of the SPI bus TTL voltage thresholds. Although Vreg is not available with the CY7C63310, 3.3 V I/O is still available. – – P1.7 GPIO Port 1 bit 7. Configured individually. TTL voltage threshold. ...
Page 8
... The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by arithmetic, logic, and shift operations. The manner in which each flag is changed is dependent upon the instruction being executed, such as AND, OR, XOR, and others. See Table 8-1 on page CY7C63310, CY7C638xx Description 13. Page [+] Feedback ...
Page 9
... Bit [7:0]: CPU Accumulator [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode Document 38-08035 Rev. *N Table 7-1 on page XIO Super – R CPU Accumulator [7:0] – – – CY7C63310, CY7C638xx Carry Zero Global – – – Page [+] Feedback ...
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... The immediate value added with the Accumulator and the result is placed in the Accumulator. MOV X 8 The immediate value moved to the X register. AND F 9 The immediate value logically ANDed with the F register and the result is placed in the F register. CY7C63310, CY7C638xx – – – – ...
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... The value in the register space at address moved to the X register. Document 38-08035 Rev. *N CY7C63310, CY7C638xx 7.2.4 Destination Direct The result of an instruction using this addressing mode is placed within the RAM memory space or the register space. Operand address that points to the location of the result. The source for the instruction is either the A register or the X register, which is specified as part of the instruction opcode ...
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... MVI instruction. The instruction using this addressing mode is two bytes in length. Table 7-16. Destination Indirect Post Increment Opcode Instruction Example MVI [8] CY7C63310, CY7C638xx Operand 1 Operand 2 Destination address Source address [8] The value in the memory location at address 8 is moved to the memory location at address 7. ...
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... MOV [expr], A – MOV [X+expr], A – MOV [expr], expr – MOV [X+expr], expr – MOV X, expr – MOV X, [expr] – MOV X, [X+expr] CY7C63310, CY7C638xx Instruction Format Flags – MOV [expr MOV – MOV MOV A, reg[expr MOV A, reg[X+expr MOV [expr], [expr] – ...
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... Reserved 0x005C Reserved 0x0060 Reserved 0x0064 Sleep timer 0x0068 Program Memory begins here (if below interrupts not used, program memory can start lower) 0x0BFF 3 KB ends here (CY7C63310) 0x0FFF 4 KB ends here (CY7C63801) 0x1FFF 8 KB ends here (CY7C638x3) CY7C63310, CY7C638xx Page [+] Feedback ...
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... Data Memory Organization The CY7C63310/638xx microcontrollers provide up to 256 bytes of data RAM. after reset 8-bit PSP Top of RAM Memory 9.3 Flash This section describes the flash block of the enCoRe II. Much of the user visible flash functionality including programming and security are implemented in the M8C Supervisory Read Only Memory (SROM) ...
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... KEY1, and KEY2 all have a value of 00h. Table 9-4. ReadBlock Parameters Name Address KEY1 0,F8h KEY2 0,F9h BLOCKID 0,FAh POINTER 0,FBh CY7C63310, CY7C638xx Description 3Ah Stack Pointer value, when SSC is executed. flash block number First of 64 addresses in SRAM where returned data must be stored. Page [+] Feedback ...
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... KEY1 and KEY2. The block number to be erased must be stored in the BLOCKID variable and the CLOCK and DELAY values must be set based on the current CPU speed. Document 38-08035 Rev. *N CY7C63310, CY7C638xx Table 9-6. EraseBlock Parameters Name Address Description ...
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... DELAY 0,FEh For a CPU speed of 12 MHz set to 56h Document 38-08035 Rev. *N CY7C63310, CY7C638xx 9.5.7 TableRead Function The TableRead function gives the user access to part specific data stored in the flash during manufacturing. It also returns a Revision ID for the die (not to be confused with the Silicon ID). ...
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... ID pointer to data buffer Clock ClockW ClockE multiplier flash macro sequence delay count temporary result code ; create 3 byte stack frame (2 + pushed A) ; save stack frame for supervisory code ;flash_OPER_KEY - 3Ah CY7C63310, CY7C638xx FDh FEh FFh Figure 9-3 Table 9-1 Page [+] Feedback ...
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... V LP mode: +12 48% ■ Document 38-08035 Rev. *N CY7C63310, CY7C638xx When using the 32 kHz oscillator, the PITMRL/H registers must be read until 2 consecutive readings match before the result is considered valid. The following firmware example assumes the developer is interested in the lower byte of the PIT. ...
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... CLK_EXT CLK_24MHz Document 38-08035 Rev. *N Figure 10-1. Clock Block Diagram CPUCLK SEL n SCALE (divide MUX n = 0-5,7) EXT CLK_USB MUX 24 MHz SEL SCALE OUT SEL SCALE MHz MHz 1 1 EXT EXT LP OSC CLK_32 32 KHz KHz CY7C63310, CY7C638xx CPU_CLK Page [+] Feedback ...
Page 22
... CLKOUT follow: Table 10-4 on page CLKIN after the optional EFTB filter ■ Internal 24 MHz Oscillator ■ Internal 32 kHz low power oscillator ■ CPUCLK after the programmable divider ■ R/W R/W R CY7C63310, CY7C638xx Gain[4:0] R/W R/W R Page [+] Feedback ...
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... Note The CPU speed selection is configured using the OSC_CR0 Register Document 38-08035 Rev kHz Bias Trim [1:0] R/W R/W R USB CLK Select Reserved R/W – – 25) (Table 10-4 on page CY7C63310, CY7C638xx kHz Freq Trim [3:0] R/W R/W R CPUCLK Select – – R 24). Page [+] Feedback ...
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... LVD and POR detection circuit is turned pin (the Sleep Duty Cycle bits in the ECO_TR are used to control CC External Clock Clock In/8 Clock In/4 Clock In/2 Clock In/1 Clock In/16 Clock In/32 Clock In/128 Reserved CY7C63310, CY7C638xx CPU Speed [2:0] R/W R/W R Page ...
Page 25
... External clock—external clock at CLKIN (P0.0) input Internal 32 kHz low power oscillator TCAPCLK Document 38-08035 Rev Reserved – – – TCAPCLK Select ITMRCLK Divider R/W R/W R CY7C63310, CY7C638xx Fine Tune Only USB Osclock Disable – R/W R ITMRCLK Select R/W R/W R Page [+] Feedback ...
Page 26
... tro Document 38-08035 Rev. *N CY7C63310, CY7C638xx The interval register (PITMR) holds the value that is loaded into the PIT counter on terminal count. The PIT counter is a down counter. The Programmable Interval Timer resolution is configurable. For example: TCAPCLK divide CPU clock (for example, TCAPCLK divide MHz CPU clock gives a frequency of 12 MHz ...
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... System Clock Configuration Status and Control 16-bit counter Prescale Mux Capture Registers 1ms Overflow timer Interrupt Capture0 Int Interrupt Controller Reserved – Table 10-3 on page 23) is forced to the Internal Oscillator, and the CY7C63310, CY7C638xx Capture1 Int CLKOUT Select - R/W R Page [+] Feedback ...
Page 28
... If an application wants to stop code execution until a reset, the preferred method is to use the HALT instruction rather than writing to this bit Normal CPU operation 1 = CPU is halted (not recommended) Note Clear. This bit is cleared only by the user and cannot be set by firmware. Document 38-08035 Rev WDRS PORS Sleep [4] [4] R/C R/C R 29. CY7C63310, CY7C638xx Reserved Stop – – R Page [+] Feedback ...
Page 29
... The Sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. The Sleep interrupt may also be used to provide periodic interrupts during non-sleep modes. CY7C63310, CY7C638xx (Table 10-4 on page ...
Page 30
... Note that in on page 31 fixed function blocks, such as flash, internal oscillator, EFTB, and bandgap, have about 15 µSec start up. The wakeup times (interrupt to CPU operational) range from 75 µS to 105 µS. CY7C63310, CY7C638xx Figure 12-1 on page 30 the Figure 12-2 Page [+] Feedback ...
Page 31
... Note In case of a self powered designs, particularly battery power, the USB suspend current specifications may not be met because the USB pins are expecting termination. Figure 12-2. Wake Up Timing Interrupt is double sampled by 32K clock and PD is negated to system CY7C63310, CY7C638xx CPU is restarted after 90ms (nominal) Page [+] Feedback ...
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... Document 38-08035 Rev PORLEV[1:0] Reserved R/W R/W – LVD Trip Point (V) Max Reserved Reserved Reserved Reserved 4.528 4.689 4.774 4.862 CY7C63310, CY7C638xx VM[2:0] R/W R/W R (Table 13-2) give the Page [+] Feedback ...
Page 33
... Internal 32 kHz Low-speed Oscillator Note This register exists in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register. Document 38-08035 Rev Reserved – – – Reserved – – – CY7C63310, CY7C638xx LVD PPOR – – – – Page [+] Feedback ...
Page 34
... Besides its use as the P0.0 GPIO, this pin is also used for an alternate function as the CLKIN pin. To configure the P0.0 pin, refer to the P0.0/CLKIN Configuration Register Document 38-08035 Rev P0.5/TIO0 P0.4/INT2 P0.3/INT1 R/W R/W R (Table 14-2 on page 37). (Table 14-1 on page 37). CY7C63310, CY7C638xx P0.2/INT0 P0.1/CLKOUT P0.0/CLKIN R/W R/W R (Table 14-3 on page 38). Page [+] Feedback ...
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... Table 19-1 on page 58 is set), a 3.3V source is placed on the pin and the GPIO function of the pin is disabled. The VREG functionality is not present in the CY7C63310 and the CY7C63801 variants μF min, 2 μF max capacitor is required on VREG output. Bit [1:0]: P1.1–P1.0/D– and D+ When the USB mode is disabled (Bit 7 in the P1.0 and P1.1 pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– ...
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... Output or SPI Use bit. The SPI function controls the output enable for its dedicated function pins when their GPIO enable bit is clear. The VREG output is not available on the CY7C63801 and CY7C63310. 14.2.9 3.3V Drive The P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI) and P1.6(SMISO) pins have an alternate voltage source from the voltage regulator. ...
Page 37
... Figure 14-1. Block Diagram of a GPIO VREG VREG GND Int Act Low TTL Thresh Reserved R/W R/W – Int Act Low TTL Thresh Reserved R/W R/W – (Table 10-1 on page CY7C63310, CY7C638xx V VREG Data Out GPIO PIN V GND Open Drain Pull-up Enable Output Enable R/W R/W R ...
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... Int Act Low TTL Thresh Reserved R/W R/W – (Table 17-7 on page Int Act Low TTL Thresh Reserved R/W R/W – CY7C63310, CY7C638xx Open Drain Pull-up Enable Output Enable R/W R/W R and Table 17-5 on page 54 Open Drain Pull-up Enable Output Enable ...
Page 39
... Reserved R/W – – for information on enabling USB. When USB is enabled, none of the (Table 14- Int Act Low TTL Threshold Reserved R/W R/W – CY7C63310, CY7C638xx Open Drain Pull-up Enable Output Enable R/W R/W R PS/2 Pull-up Output Enable Enable – R/W R/W ...
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... Table 15-2 on page 42 Int Act Low Reserved High Sink R/W – R Int Act Low TTL Thresh Reserved R/W R/W – CY7C63310, CY7C638xx Open Drain Pull-up Enable Output Enable R/W R/W R Open Drain Pull-up Enable Output Enable R/W R/W R Open Drain ...
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... SPI clocks to manage the buffers: to empty the receiver buffer or to refill the transmit holding register. Failure to meet this timing requirement results in incorrect data transfer. Document 38-08035 Rev Int Act Low TTL Thresh Reserved R/W R/W – SPIData[7:0] R/W R/W R CY7C63310, CY7C638xx Open Drain Pull-up Enable Output Enable R/W R/W R R/W R/W R Page [+] Feedback ...
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... Document 38-08035 Rev Comm Mode CPOL R/W R/W R Table 15-4 on page 43 40), the input/output direction of pins P1.3, P1.5, and P1.6 is set 24 MHz 4 MHz 2 MHz 500 kHz 250 kHz CY7C63310, CY7C638xx CPHA SCLK Select R/W R/W R shows the timing for the Page [+] Feedback ...
Page 43
... SSEL DAT SCLK SSEL DAT SSEL DAT A Document 38-08035 Rev. *N Diagram LSB Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 X LSB Bit 2 Bit 3 Bit 4 Bit 5 X LSB Bit 2 Bit 3 Bit 4 Bit 5 CY7C63310, CY7C638xx Bit 7 MSB X Bit 6 Bit 7 MSB Bit 6 Bit 7 MSB X Page [+] Feedback ...
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... Document 38-08035 Rev verflow Interrupt/W rap Interrupt 16-bit Free R unning C ounter 1024µ Interrupt Free running Timer [7:0] R/W R/W R Free-running Timer [15:8] R/W R/W R CY7C63310, CY7C638xx R/W R/W R R/W R/W R Page [+] Feedback ...
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... Document 38-08035 Rev Capture 0 Rising [7:0] R/W R/W R Capture 1 Rising [7:0] R/W R/W R Capture 0 Falling [7:0] R/W R/W R Capture 1 Falling [7:0] R/W R/W R Prog Interval Timer [7: CY7C63310, CY7C638xx R/W R/W R R/W R/W R R/W R/W R R/W R/W R Page [+] Feedback ...
Page 46
... This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write the lower byte first then the higher nibble. Figure 16-2. Programmable Interval Timer Block Diagram Document 38-08035 Rev – – Prog Interval [7:0] R/W R/W R – – R CY7C63310, CY7C638xx Prog Interval Timer [11: R/W R/W R Prog Interval[11:8] R/W R/W R Page [+] Feedback ...
Page 47
... Capture 0 16-bit mode is enabled. Capture 1 is disabled and the Capture 1 rising and falling registers are used as an extension to the Capture 0 registers–extending them to 16 bits Bit [2:0]: Reserved Document 38-08035 Rev Cap0 16bit Enable R/W R/W R CY7C63310, CY7C638xx Reserved – – – Page [+] Feedback ...
Page 48
... Interrupt status bit. Document 38-08035 Rev Cap1 Fall Cap1 Rise Enable Enable – – R TIO1 Fall TIO1 Rise Active Active – – R CY7C63310, CY7C638xx Cap0 Fall Cap0 Rise Enable Enable R/W R/W R TIO0 Fall TIO0 Rise Active Active R/W R/W R Page ...
Page 49
... Figure 16-3. Timer Functional Sequence Diagram Document 38-08035 Rev. *N CY7C63310, CY7C638xx Page [+] Feedback ...
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... ACBE ACBF ACC0 running counter Figure 16-5. Memory Mapped Registers Read/Write Timing Diagram clk_sys rd_wrn Valid Addr rdata wdata Document 38-08035 Rev. *N 12-bit programmable timer load timing 16-bit free running counter loading timing CY7C63310, CY7C638xx Page [+] Feedback ...
Page 51
... Reserved 25 0064h Sleep timer Document 38-08035 Rev. *N CY7C63310, CY7C638xx 17.1 Architectural Description An interrupt is posted when its interrupt conditions occur. This results in the flip-flop in Figure 17-1 on page 52 The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register. ...
Page 52
... CPU clock cycles before the ISR begins is as follows cycles for JMP to finish) + (13 cycles for interrupt routine cycles for LJMP cycles. In the previous example MHz, 25 clock cycles take 1.042 μs. CY7C63310, CY7C638xx Interrupt Vector Interrupt Request M8C Core CPU_F[0] ...
Page 53
... INT_CLRx register, when ENSWINT is set, causes an interrupt to post for the corresponding interrupt. Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interac- tions that are sometimes necessary to create a hardware only interrupt. CY7C63310, CY7C638xx SPI Transmit INT0 ...
Page 54
... Document 38-08035 Rev Reserved – – – GPIO Port 3 GPIO Port 2 PS/2 Data Low Int Enable Int Enable Int Enable R/W R/W R CY7C63310, CY7C638xx – – – INT2 16-bit Counter TCAP1 Int Enable Wrap Int Enable Int Enable R/W R/W R Page ...
Page 55
... Bit 0: USB EP0 Interrupt Enable 0 = Mask EP0 interrupt 1 = Unmask EP0 interrupt Document 38-08035 Rev Timer USB Active USB Reset Int Enable Int Enable Int Enable R/W R/W R CY7C63310, CY7C638xx USB EP2 USB EP1 USB EP0 Int Enable Int Enable Int Enable R/W R/W R Page [+] Feedback ...
Page 56
... Writing to this register clears all pending interrupts. Document 38-08035 Rev INT1 GPIO Port 0 SPI Receive Int Enable Int Enable Int Enable R/W R/W R Pending Interrupt [7:0] R/W R/W R CY7C63310, CY7C638xx SPI Transmit INT0 POR/LVD Int Enable Int Enable Int Enable R/W R/W R R/W R/W R Page [+] Feedback ...
Page 57
... Note Use of the alternate drive on pins P1.3–P1.6 requires that the VREG Enable bit be set to enable the regulator and provide the alternate voltage. Document 38-08035 Rev Reserved – – – below 4.35V—although no damage or irregularities occur enabled below 4.35 V. CY7C63310, CY7C638xx Keep Alive VREG Enable – R/W R above 4. ...
Page 58
... Firmware is required to handle the rest of the USB interface with the following tasks: Coordinate enumeration by decoding USB device requests. ■ Fill and empty the FIFOs. ■ Suspend and Resume coordination. ■ Verify and select Data toggle values. ■ CY7C63310, CY7C638xx USB Force State – – R ...
Page 59
... For Endpoint 0 Count Register, when the count updates from a SETUP or OUT transaction, the count register locks and cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on it. Document 38-08035 Rev Device Address[6:0] R/W R/W R Reserved R/W R/W R CY7C63310, CY7C638xx R/W R/W R Byte Count[3:0] R/W R/W R Page [+] Feedback ...
Page 60
... USB SIE responds to traffic, and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. Note Clear. This bit is cleared only by the user and cannot be set by firmware. Document 38-08035 Rev OUT Received ACK’d Trans [5] [5] R/C R/C R CY7C63310, CY7C638xx Mode[3:0] R/W R/W R Page [+] Feedback ...
Page 61
... Transaction R/W R/C (Note 4) R Endpoint 0 Data Buffer [7:0] R/W R/W R/W Unknown Unknown Unknown Endpoint 1 Data Buffer [7:0] R/W R/W R/W Unknown Unknown Unknown CY7C63310, CY7C638xx Mode[3:0] R/W R/W R R/W R/W R/W Unknown Unknown Unknown R/W R/W R/W Unknown Unknown ...
Page 62
... SIE responds to different tokens that the host sends to the endpoints. For example, if the Mode Bits [3:0] of the Endpoint 0 Mode Register are set to '0001', which is NAK IN/OUT mode, the SIE sends an ACK handshake in response to SETUP tokens and NAK any IN or OUT tokens. CY7C63310, CY7C638xx R/W ...
Page 63
... STALL 0011 STALL 0011 ACK 1 1 0010 1 1 ACK 1 1 0001 update 1 STALL 0011 CY7C63310, CY7C638xx EP0 Interrupt Comments Ignore All junk Ignore junk Ignore update data Yes ACK SETUP Stall IN Ignore Ignore Stall OUT junk Ignore junk Ignore ...
Page 64
... 0011 STALL 0011 ACK 1 1000 update 1 STALL NAK TX 1 1100 CY7C63310, CY7C638xx EP0 Interrupt Comments Yes Bad status Yes Bad status 2 Yes Good status junk Ignore junk Ignore update data Yes ACK SETUP Host not ACK'd Yes Host ACK'd ...
Page 65
... Free Running Timer [7:0] Free Running Timer [15:8] Capture 0 Rising [7:0] Capture 1 Rising [7:0] Capture 0 Falling [7:0] Capture 1 Falling [7:0] Prog Interval Timer [7:0] Prog Interval Timer [11:8] Prog Interval [7:0] Prog Interval [11:8] CY7C63310, CY7C638xx EP0 Interrupt Comments Stall IN Ignore If Enabled NAK R/W Default P0 ...
Page 66
... Int Enable Counter Enable Int Enable 1-ms USB Active USB Reset USB EP2 USB EP1 Timer Int Enable Int Enable Int Enable Int Enable CY7C63310, CY7C638xx 1 0 R/W Default bbbbb--- 00000000 Cap0 Rise ----bbbb 00000000 Active Active Cap0 Rise ----bbbb 00000000 ...
Page 67
... Program Counter [15:8] Stack Pointer [7:0] XOI Super Carry WDRS PORS Sleep Reserved Reserved Sleep Timer [1:0] CPU Speed [2:0] PORLEV[1:0] Reserved VM[2:0] Reserved Reserved CY7C63310, CY7C638xx 1 0 R/W Default INT0 POR/LVD bbbbbbbb 00000000 Int Enable bbbbbbbb 00000000 wwwwwwww 00000000 -------- 00000000 -------- ...
Page 68
... Firmware can monitor for VLTCMP to clear within the normal ■ application main loop. Debounce the indication to ensure voltage is above the set ■ point. Shift the POR to the high set point. ■ Shift the CPU to 24 MHz. ■ CY7C63310, CY7C638xx 24 MHz Page [+] Feedback ...
Page 69
... I < 125 mA (3.3V ± 8%) VREG °C V > 4. < temp < 40 ° < I < (3.3V ± 4%) VREG °C – – – ± 5% Ohm enabled UP CY7C63310, CY7C638xx Min Typical Max Unit 4.0 – 5.5 V 4.35 – 5.25 V 4.0 – 5.5 V 4.75 – 5.5 ...
Page 70
... Conditions – External clock is the source of the CPUCLK External clock is not the source of the CPUCLK No USB present With USB present Normal mode Low power mode 100 MHz at CLOAD = 1 μF CY7C63310, CY7C638xx Min Typical Max Unit 0.2 – – V 0.8 – 2 ...
Page 71
... SHD T Slave data output time SDO T Slave data output time, SDO1 First bit with CPHA = 0 T Slave select setup time SSS T Slave select hold time SSH Document 38-08035 Rev. *N CY7C63310, CY7C638xx Conditions C = 200 pF LOAD C = 600 pF LOAD C = 200 pF LOAD C = 600 pF LOAD – ...
Page 72
... Document 38-08035 Rev. *N Figure 28-1. Clock Timing T CYC Figure 28-2. GPIO Timing Diagram T T R_GPIO F_GPIO Figure 28-3. USB Data Signal Timing 90% 90% 10% 10% Figure 28-4. Receiver Jitter Tolerance JR1 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 CY7C63310, CY7C638xx T JR2 Page [+] Feedback ...
Page 73
... Document 38-08035 Rev. *N Crossover Point Extended Crossover Point Diff. Data to SE0 Skew PERIOD DEOP Figure 28-6. Differential Data Jitter Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions PERIOD xJR2 CY7C63310, CY7C638xx Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page [+] Feedback ...
Page 74
... MISO Document 38-08035 Rev. *N Figure 28-7. SPI Master Timing, CPHA = 1 (SS is under firmware control in SPI Master mode) T SCKL MSB T MHD Figure 28-8. SPI Slave Timing, CPHA = 1 T SCKL MSB T SSU SHD MSB CY7C63310, CY7C638xx LSB LSB T SSH LSB LSB Page [+] Feedback ...
Page 75
... SSU SHD T SDO1 MISO MSB Document 38-08035 Rev. *N Figure 28-9. SPI Master Timing, CPHA = 0 (SS is under firmware control in SPI Master mode) T SCKL T MDO Figure 28-10. SPI Slave Timing, CPHA = 0 T SCKL T SDO CY7C63310, CY7C638xx LSB LSB T SSH LSB LSB Page [+] Feedback ...
Page 76
... Sawn, Tape and Reel Temperature Grade Commercial Industrial Pb-free Package Type Family Technology: CMOS Marketing Code SRAM Company ID Cypress Min Typical – 125 See package label – CY7C63310, CY7C638xx Package Type Max Unit See package label °C 72 hours Page [+] Feedback ...
Page 77
... Package Diagrams Document 38-08035 Rev. *N Figure 31-1. 16-Pin (300-Mil) Molded DIP P1 Figure 31-2. 16-Pin (150-Mil) SOIC S16.15 CY7C63310, CY7C638xx 51-85009 *B 51-85068 *C Page [+] Feedback ...
Page 78
... Document 38-08035 Rev. *N Figure 31-3. 18-Pin (300-Mil) Molded DIP P3 Figure 31-4. 18-Pin (300-Mil) Molded SOIC S3 CY7C63310, CY7C638xx 51-85010 *C 51-85023 *C Page [+] Feedback ...
Page 79
... S Document 38-08035 Rev. *N Figure 31-5. 24-Pin (300-Mil) SOIC S13 Figure 31-6. 24-Pin QSOP O241 CY7C63310, CY7C638xx 51-85025 *E 51-85055 *C Page [+] Feedback ...
Page 80
... Figure 31-7. 24-Pin QFN 4X4X0.55 mm LQ24 A 2.65X2.65X EPAD (Sawn) Document 38-08035 Rev. *N Figure 31-8. 32-Pin QFN Package CY7C63310, CY7C638xx 001-13937 *C 51-85188 *D Page [+] Feedback ...
Page 81
... Document 38-08035 Rev. *N Figure 31-9. 32-Pin Sawn QFN Package CY7C63310, CY7C638xx 001-30999 *C Page [+] Feedback ...
Page 82
... CE chip enable I/O input/output OE output enable SRAM static random access memory TSOP thin small outline package WE write enable Document 38-08035 Rev. *N CY7C63310, CY7C638xx 33. Document Conventions Units of Measure Symbol Unit of Measure ns nano seconds V volts µA micro amperes mA milli amperes pF pico Farad ° ...
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... Document History Page Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Submis- Revision ECN No. Change sion Date ** 131323 XGR 12/11/03 *A 221881 KKU See ECN *B 271232 BON See ECN *C 299179 BON See ECN *D 322053 TVR ...
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... Document History Page Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller Document Number: 38-08035 Orig. of Submis- Revision ECN No. Change sion Date *G 424790 TYJ See ECN *H 491711 TYJ See ECN *I 504691 TYJ See ECN Document 38-08035 Rev. *N (continued) Description of Change ...
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... Updated to data sheet template *E. Added Package Handling information Added partnumber CY7C63803-LQXC to the ordering information table and added package diagram (spec 001-13937) Removed inactive parts from ordering information table. CY7C63310-PXC CY7C63801-PXC CY7C63833-LFXC Updated package diagrams. Added Ordering Code Definition, Acronyms, and Document Conventions. ...
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... Document 38-08035 Rev. *N PSoC Designer™ trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised March 18, 2011 CY7C63310 CY7C638xx PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...