CY7C67200-48BAXI Cypress Semiconductor Corp, CY7C67200-48BAXI Datasheet
CY7C67200-48BAXI
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CY7C67200-48BAXI
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CY7C67200-48BAXI Summary of contents
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... Mass storage devices Timer 0 Timer 1 CY16 16-bit RISC CORE 4Kx16 8Kx16 ROM BIOS RAM • 198 Champion Court • San Jose CY7C67200 On-The-Go UART I/F I2C EEPROM I/F HSS I/F GPIO [24:0] SPI I/F HPI I/F GPIO , CA 95134-1709 • 408-943-2600 ...
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... Introduction EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable IO interface block allowing a wide range of interface options ...
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... Unused GPIO pins must be configured as outputs and driven low. UART Interface EZ-OTG has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used development port or for other interface requirements. The UART interface is exposed through GPIO pins CY7C67200 Pin Number Page [+] Feedback ...
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... Selectable CTS/RTS hardware signal handshake protocol • Selectable XON/XOFF software handshake protocol • Programmable Receive interrupt, Block Transfer Done interrupts • Complete access to internal memory HSS Pins Table 8. HSS Interface Pins Pin Name CTS RTS RX TX CY7C67200 Pin Number Pin Number Page ...
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... USB OTG specification for a dual-role device. The minimum value µF. There are no restrictions on the type of capacitor D5 for C2 the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left uncon- C5 nected. CY7C67200 [1, 2] (continued) Pin Number ...
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... If an oscillator is used instead of a crystal circuit, connect it to XTALIN and leave XTALOUT uncon- nected. For further information on the crystal requirements, see Table 39, “Crystal Requirements,” on page Figure 4. Crystal Interface XTALIN CY7C67200 XTALOUT CY7C67200 3.0V to 3.6V Power Supply Pin Number F1 E2 65. Y1 12MHz ...
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... If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral. — If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host. • Ports 1B, 2A, and 2B default as USB peripheral ports. • All other pins remain INPUT pins. CY7C67200 Table 14 for for booting into standalone mode. Page [+] Feedback ...
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... Firmware must disable the charge pump (OTG Control register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS will only drop to V diode drops). • Booster circuit is turned off. • USB transceivers is turned off. • CPU suspends until a programmable wakeup event. CY7C67200 Reset Logic 22pf XIN 12MHz XOUT ...
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... CC 0x0200- 0x02FF 0x0300- 0x030F 0x0310- 0x03FF 0x0400- 0x04A2 0x04A4- 0x3FFF 0xC000- 0xC0FF Figure 6. 0xE000- 0xFFFF CY7C67200 Internal Memory HW INTs SW INTs Primary Registers Swap Registers HPI Int / Mailbox LCP Variables USB Registers Slave Setup Packet BIOS Stack USB Slave & OTG ...
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... Carry/Borrow occurred 0: Carry/Borrow did not occur Zero Flag (Bit 0) The Zero Flag bit indicates if an instruction execution resulted in a ‘0’. 1: Zero occurred 0: Zero did not occur CY7C67200 Address R/W 0xC000 R 0xC002 R/W 0xC004 ...
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... Reserved All reserved bits must be written as ‘0’. Figure 9. Revision Register Revision... ...Revision Revision (Bits [15:0]) The Revision field contains the silicon revision number. CY7C67200 R/W R/W R Binary Value 0000 0001 0000 0000 0000 0000 0001 1100 0000 0001 0001 1100 10 9 ...
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... MHz/8 1000 48 MHz/9 1001 48 MHz/10 1010 48 MHz/11 1011 48 MHz/12 1100 48 MHz/13 1101 48 MHz/14 1110 48 MHz/15 1111 48 MHz/16 Reserved All reserved bits must be written as ‘0’. Document #: 38-08014 Rev. *G Figure 10. CPU Speed Register Reserved... - - - R CY7C67200 CPU Speed R/W R/W R Table 18. Page [+] Feedback ...
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... USB transceivers are powered down. All counters and timers are paused but will retain their values. SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution resumes within 0.5 ms. 1: Enable Sleep Mode 0: No Function CY7C67200 Reserved HSS SPI ...
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... HPI: Incoming Mailbox hardware interrupt. 1: Enable MBXI interrupt Host 2 0: Disable MBXI interrupt Out Mailbox Interrupt Enable (Bit 5) The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt. 1: Enable MBXO interrupt 0: Disable MBXO interrupt CY7C67200 Reserved Host/Device 2 Host/Device 1 Interrupt Interrupt Enable ...
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... TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0 interrupts are cleared. 1: Enable TM0 interrupt 0: Disable TM0 interrupt Reserved All reserved bits must be written as ‘0’. Figure 13. Breakpoint Register Address... R/W R/W R ...Address R/W R/W R CY7C67200 R/W R/W R R/W R/W R Page [+] Feedback ...
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... All reserved bits must be written as ‘0’. Timer Registers There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized in Table Table 20.Timer Registers Register Name Watchdog Timer Register Timer 0 Register Timer 1 Register CY7C67200 Reserved... - - - ...
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... If this time The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid a Watchdog trigger 1: Reset Count Reserved 1.4 ms All reserved bits must be written as ‘0’. 5.5 ms 22.0 ms 66.0 ms CY7C67200 R/W R/W R ...
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... Section “USB Device Only Registers” on page Address (SIE1/SIE2) 0xC08A/0xC0AA Figure 17. USB n Control Register Port A Port A Reserved D+ Status D– Status Reserved Port A Force D± State - R/W R CY7C67200 R/W R/W R R/W R/W R Section “USB Host Only Registers” on page 28. R/W R LOA Mode Reserved Select ...
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... Host n PID Register Host n Count Result Register Host n Device Address Register Host n Interrupt Enable Register Host n Status Register Host n SOF/EOP Count Register Host n SOF/EOP Counter Register Host n Frame Register CY7C67200 Function LSB 0 Normal Operation 1 Force USB Reset, SE0 State 0 Force J-State ...
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... Enable Isochronous transaction 0: Disable Isochronous transaction Arm Enable (Bit 0) The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is complete. 1: Arm endpoint and begin transaction 0: Endpoint disarmed Reserved All reserved bits must be written as ‘0’. CY7C67200 ...
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... Count (Bits [9:0]) The Count field sets the value for the current transaction data packet length. This value is retained when switching between host and device mode, and back again. Reserved All reserved bits must be written as ‘0’. CY7C67200 R/W R/W R/W ...
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... Timeout, receiving a NAK, or receiving a STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in an Error flag along with receiving incorrect packet types. 1: Error detected 0: No error detected CY7C67200 Underflow Reserved Flag ...
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... Table 26.PID Select Definition (continued) PID TYPE PREAMBLE NAK STALL 26. ACK and NAK DATA0 DATA1 Endpoint Select (Bits [3:0]) The Endpoint field allows addressing different endpoints. Reserved All reserved bits must be written as ‘0’. CY7C67200 Endpoint Select PID Select [7:4] 1100 (C Hex) ...
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... Figure 24. Host n Device Address Register Reserved... - - - Address Address (Bits [6:0]) The Address field contains the value of the USB address for the next device that the host is going to communicate with. This value must be written by firmware. Reserved All reserved bits must be written as ‘0’. CY7C67200 ...
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... ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B. 1: Enable USB Transfer Done interrupt 0: Disable USB Transfer Done interrupt Reserved All reserved bits must be written as ‘0’. CY7C67200 SOF/EOP Reserved Interrupt Enable ...
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... Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B. 1: Interrupt triggered 0: Interrupt did not trigger CY7C67200 SOF/EOP Reserved ...
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... Count (Bits [13:0]) The Count field sets the SOF/EOP counter duration. Reserved All reserved bits must be written as ‘0’ Counter... ...Counter Counter (Bits [13:0]) The Counter field contains the current value of the SOF/EOP down counter. CY7C67200 Count... R/W R/W R R/W R/W R ...
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... Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers for each Device Port for a total of 16 registers per set. The USB Device Only registers are covered in this section and summarized in Table CY7C67200 Frame... R ...
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... Enable transfers to an endpoint 0: Do not allow transfers to an endpoint Arm Enable (Bit 0) The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete. 1: Arm endpoint 0: Endpoint disarmed Reserved All reserved bits must be written as ‘0’. CY7C67200 ...
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... Figure 32. Device n Endpoint n Count Register Bit # 15 14 Field Read/Write - - Default X X Bit # 7 6 Field Read/Write R/W R/W Default X X Document #: 38-08014 Rev Address... R/W R/W R ...Address R/W R/W R Reserved - - - ...Count R/W R/W R CY7C67200 R/W R/W R R/W R/W R Count... - R/W R R/W R/W R Page [+] Feedback ...
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... Underflow condition occurred 0: Underflow condition did not occur OUT Exception Flag (Bit 9) The OUT Exception Flag bit indicates when the device received an OUT packet when armed for an IN. 1: Received OUT when armed for IN 0: Received IN when armed for IN CY7C67200 OUT IN Flag ...
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... Overflow and Underflow are not considered errors and do not affect this bit. 1: Error occurred 0: Error did not occur ACK Flag (Bit 0) The ACK Flag bit indicates whether the last transaction was ACKed. 1: ACK occurred 0: ACK did not occur CY7C67200 Page [+] Feedback ...
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... Result [15:10] is set to ‘111111’, a 2’s complement value indicating the additional byte count of the received packet underflow condition occurs, Result [15:0] indicates the excess byte count (number of bytes not used). Reserved All reserved bits must be written as ‘0’. CY7C67200 R/W R/W ...
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... ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP6 Transaction Done interrupt 0: Disable EP6 Transaction Done interrupt CY7C67200 Reserved SOF/EOP ...
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... Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt. 1: Enable EP0 Transaction Done interrupt 0: Disable EP0 Transaction Done interrupt Reserved All reserved bits must be written as ‘0’. CY7C67200 Page [+] Feedback ...
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... This bit is only available for Device 1 and is a reserved bit in Device 2. 1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP Interrupt Flag (Bit 9) The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt has triggered. 1: Interrupt triggered 0: Interrupt did not trigger CY7C67200 ...
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... Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests. 1: Interrupt triggered 0: Interrupt did not trigger Reserved All reserved bits must be written as ‘0’. CY7C67200 Page [+] Feedback ...
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... Count (Bits [13:0]) The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly. Reserved All reserved bits must be written as ‘0’. CY7C67200 Frame... R R ...
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... OTG VBus is less than 0.8V ID Status (Bit 1) The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A. 1: OTG ID Pin is not connected directly to ground (>10K ohm) 0: OTG ID Pin is connected directly ground (< 10 ohm) CY7C67200 Address R/W C098H R/W 10 ...
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... SCAN – (HW) Scan diagnostic. For produc- tion test only. Not for normal operation 101 HPI – Host Port Interface 100 Reserved 011 Reserved 010 Reserved 001 Reserved 000 GPIO – General Purpose Input Output CY7C67200 R/W R/W R/W R R/W R Mode Select ...
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... Figure 42. GPIO 0 Output Data Register GPIO13 GPIO12 GPIO11 R/W R/W R GPIO5 GPIO4 GPIO3 R/W R/W R Figure 43. GPIO n Output Data Register GPIO29 Reserved R GPIO21 GPIO20 GPIO19 R/W R/W R CY7C67200 GPIO10 GPIO9 GPIO8 R/W R/W R GPIO2 GPIO1 GPIO0 R/W R/W R GPIO24 - - R Reserved - - - Page [+] Feedback ...
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... GPIO5 GPIO4 GPIO3 Figure 45. GPIO 1 Input Data Register GPIO29 Reserved GPIO21 GPIO20 GPIO19 Figure 46. GPIO 0 Direction Register GPIO13 GPIO12 GPIO11 R/W R/W R GPIO5 GPIO4 GPIO3 R/W R/W R CY7C67200 GPIO10 GPIO9 GPIO8 GPIO2 GPIO1 GPIO0 GPIO24 - - Reserved - - - GPIO10 GPIO9 GPIO8 R/W R/W R ...
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... Document #: 38-08014 Rev. *G Figure 47. GPIO 1 Direction Register GPIO29 Reserved R/W R/W R GPIO21 GPIO20 GPIO19 R/W R/W R Address 0xC070 0xC072 0xC074 0xC076 0xC078 0xC07A 0xC07C 0xC07E CY7C67200 GPIO24 R/W R/W R Reserved R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W Page [+] Feedback ...
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... One Stop Bit (Bit 5) The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may vary and does not need to be fixed. 1: One stop bit 0: Two stop bits CY7C67200 CTS Receive ...
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... The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty. 1: HSS receive FIFO is not empty (one or more bytes is reading for reading) 0: HSS receive FIFO is empty Figure 49. HSS Baud Rate Register R/W R ...Baud R/W R/W R CY7C67200 Baud... R/W R/W R R/W R/W R Page [+] Feedback ...
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... The Data field contains the data received transmitted on the HSS port. Reserved All reserved bits must be written as ‘0’. Document #: 38-08014 Rev. *G Figure 50. HSS Transmit Gap Register Reserved - - - Transmit Gap Select R/W R/W R Figure 51. HSS Data Register Reserved - - - Data R/W R/W R CY7C67200 R/W R/W R R/W R/W R Page [+] Feedback ...
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... All reserved bits must be written as ‘0’. Document #: 38-08014 Rev. *G Figure 52. HSS Receive Address Register Address... R/W R/W R ...Address R/W R/W R Figure 53. HSS Receive Counter Register Reserved - - - ...Counter R/W R/W R CY7C67200 R/W R/W R R/W R/W R Counter... - R/W R R/W R/W R Page [+] Feedback ...
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... HPI status port which can be address over HPI. Each of these registers is covered in this section and are summarized in Table Table 32.HPI Registers Register Name HPI Breakpoint Register Interrupt Routing Register SIE1msg Register SIE2msg Register HPI Mailbox Register CY7C67200 R/W R/W R ...
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... CPU. 1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to HPI Enable (Bit 13) The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port. 1: Route signal to HPI port 0: Do not route signal to HPI port CY7C67200 ...
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... When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. CY7C67200 Page [+] Feedback ...
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... TX Empty interrupt is automatically cleared when the CY7C67200 writes to this register. In addition, when the CY7C67200 writes to this register, the HPI_INTR signal on the HPI port asserts signaling the external processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from this register ...
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... The SIE1msg Flag bit is a read-only bit that indicates if the CY7C67200 CPU has written to the SIE1msg register. This bit is cleared on an HPI read. 1: The SIE1msg register has been written by the CY7C67200 CPU 0: The SIE1msg register has not been written by the CY7C67200 CPU ...
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... Figure 61. SPI Configuration Register SCK Polarity Scale Select Select R/W R/W R Enable R/W R/W R CY7C67200 Table 33. R/W R/W R/W R R/W R/W R/W R/W R/W R/W R Reserved R/W R Delay Select R/W R/W R/W ...
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... SS LOW to SCK active, SCK inactive to SS HIGH, SS HIGH 8 MHz time. This field only applies to master mode. 6 MHz 4 MHz 3 MHz 2 MHz 1.5 MHz 1 MHz 750 KHz 500 KHz 375 KHz 250 KHz 375 KHz 250 KHz 375 KHz 250 KHz CY7C67200 Page [+] Feedback ...
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... Transmit Bit Length (Bits [5:3]) The Transmit Bit Length field controls whether a full byte or partial byte transmitted. If Transmit Bit Length is ‘000’, a full byte is transmitted. If Transmit Bit Length is ‘001’ to ‘111’, the value indicates the number of bits that will be transmitted. CY7C67200 Read ...
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... Indicates FIFO error 0: Indicates no FIFO error Receive Interrupt Flag (Bit 2) The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt has triggered. 1: Indicates a byte mode receive interrupt has triggered 0: Indicates a byte mode receive interrupt has not triggered CY7C67200 ...
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... No function Reserved All reserved bits must be written as ‘0’. Figure 66. SPI CRC Control Register CRC CRC Receive Enable Clear CRC R/W R/W R ...Reserved - - - Table 35.CRC Mode Definition CRCMode [9: CY7C67200 Transmit Transfer Interrupt Clear Interrupt Clear - One in Zero in Reserved... CRC CRC ...
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... CRC value is not all ones 0: CRC value is all ones Reserved All reserved bits must be written as ‘0’. Figure 67. SPI CRC Value Register CRC... R/W R/W R ...CRC R/W R/W R Figure 68. SPI Data Register Reserved - - - Data R/W R/W R CY7C67200 R/W R/W R R/W R/W R R/W R/W R Page [+] Feedback ...
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... All reserved bits must be written as ‘0’. Document #: 38-08014 Rev. *G Figure 69. SPI Transmit Address Register Address... R/W R/W R ...Address R/W R/W R Figure 70. SPI Transmit Count Register Reserved - - - ...Count R/W R/W R CY7C67200 R/W R/W R R/W R/W R Count... R/W R/W R R/W R/W R Page [+] Feedback ...
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... Document #: 38-08014 Rev. *G Figure 71. SPI Receive Address Register Address... R/W R/W R ...Address R/W R/W R Figure 72. SPI Receive Count Register Reserved - - - ...Count R/W R/W R Address 0xC0E0 0xC0E2 0xC0E4 CY7C67200 R/W R/W R R/W R/W R Count... R/W R/W R R/W R/W R R/W R/W R R/W Page [+] Feedback ...
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... Enable UART 0: Disable UART. This allows GPIO6 and GPIO7 to be used for general use Reserved All reserved bits must be written as ‘0’. Figure 74. UART Status Register Reserved... - - - ...Reserved - - - CY7C67200 Baud UART Select Enable R/W R/W R Baud Rate Baud Rate w/DIV8 = 0 w/DIV8 = 1 115 ...
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... UART Data register (to be transmitted). This bit will automatically be cleared to ‘0’ after the data is transmitted. 1: Transmit buffer full (transmit busy) 0: Transmit buffer is empty and ready for a new byte of data Figure 75. UART Data Register Reserved - - - Data R/W R/W R CY7C67200 R/W R/W R Page [+] Feedback ...
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... Pin Diagram The following describes the CY7C67200 48-pin FBGA. Figure 76. EZ-OTG Pin Diagram GPIO3/D3 GND GPIO1/ AGND GPIO0/D0 GPIO4/ GPIO2/D2 OTGVBUS DM2A CSWITCHA CSWITCHB DP2A BOOSTGND VSWITCH DP1A BOOSTVCC DM1A GPIO30/SDA AVCC XTALOUT XTALIN GPIO31/SCL GND VCC Pin Descriptions Table 38.Pin Descriptions ...
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... D1: D1 for HPI IO GPIO0: General Purpose IO D0: D0 for HPI IO USB Port 1A D– IO USB Port USB Port 2A D– IO USB Port 2A D+ Input Crystal Input or Direct Clock Input Output Crystal output. Leave floating if direct clock source is used. Input Reset CY7C67200 Page [+] Feedback ...
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... Analog Charge Pump Capacitor Analog Charge Pump Capacitor Power USB Power Ground USB Ground Power Main V CC Ground Main Ground Min. –500 20 to provide a nominal 3.3V V supply CY7C67200 Description + 0.5V CC Typical Max. Unit 12 MHz +500 PPM 33 pF 500 µ Page [+] Feedback ...
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... Conditions 8 mA< I < LOAD LOAD < 5.25V BUS OTGVBUS not driven LOAD LOAD LOAD LOAD 0V< V < 5.25V BUS values when only one transceiver is powered. CY7C67200 Min. Typ. Max. Unit 3.0 3.3 3.6 V 2.7 3.6 V 2.0 5.5 V 0.8 V µA –10.0 +10.0 2 ...
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... IOACT Note 9. Clock is 12 MHz nominal. Document #: 38-08014 Rev. *G Conditions mA, VCC = 3.3V LOAD V is not being driven BUS Pull-up voltage = 3.0V t RESET t IOACT Reset Timing Min. 16 200 CY7C67200 Min. Typ. Max. Unit 0.8 2.0 V 0.8 4.0 V 0.2 0 Ω 14.25 24.8 40 100 kΩ ...
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... FALL RISE Clock Timing Min. Typ. 12.0 1.5 3.0 83.17 83. LOW HIGH SU.DAT t HD.DAT t DH Min. Typical 1300 600 900 1300 600 600 0 100 600 0 CY7C67200 Max. Unit MHz 3 5 BUF t SU.STO Max. Unit 400 kHz 300 ns 300 ...
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... Data Setup DSU t Write Data Hold WDH t Write Pulse Width WP t Write Cycle Time CYC Note 11 system clock period = 1/48 MHz. Document #: 38-08014 Rev CYC CSH t t DSU WDH Min. Typical –1 –1 –1 – CY7C67200 Max. Unit [11] T [11] T Page [+] Feedback ...
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... Read Data Hold, relative to the earlier of HPI_nRD RDH rising or HPI_nCS rising t Read Pulse Width RP t Read Cycle Time CYC Document #: 38-08014 Rev CYC CSH t RDH t t ACC RDH Min. Typ. –1 –1 –1 – CY7C67200 Max. Unit [11 [11] T [11] T Page [+] Feedback ...
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... STOP bit. (BT = bit period GAP bit 1 bit 2 bit 3 bit 4 bit +/- 5% CY7C67200 CPU may start another BYTE transmit right after TxRdy goes high bit 4 bit 5 bit 6 bit 7 stop bit start bit start of last data bit to TxRdy high: programmable 0 min max ...
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... HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit. HSS_RTS is deasserted in the third data bit time. An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit. Document #: 38-08014 Rev. *G CY7C67200 tCTShold tCTSsetup Start of transmission not delayed by HSS_CTS ...
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... GPIO14 GPIO13 GPIO12 GPIO11 GPIO6 GPIO5 GPIO4 GPIO3 GPIO14 GPIO13 GPIO12 GPIO11 GPIO6 GPIO5 GPIO4 GPIO3 CY7C67200 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low 0000 0000 0000 0000 SOF/EOP1 to Reset2 to HPI HPI Swap 1 0001 0100 CPU Enable Enable ...
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... Timeout Inter- Enable rupt Enable EP6 EP5 EP4 EP3 Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Address CY7C67200 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low GPIO24 0000 0000 Reserved 0000 0000 GPIO24 0000 0000 Reserved 0000 0000 ...
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... Enable Enable FIFO Byte FullDuplex SS Init Mode Manual Receive Transmit Bit Length Full Reserved CRC Enable CRC Clear Receive CRC One in CRC CY7C67200 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low SOF/EOP Reserved xxxx xxxx Interrupt Flag Port A Reserved ...
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... Scale Baud Select Select ID Reserved SOF/EOP2 Reserved Flag Flag Resume1 SIE2msg SIE1msg Done2 Flag Flag CY7C67200 Bit 10 Bit 9 Bit 8 Default High Bit 2 Bit 1 Bit 0 Default Low xxxx xxxx xxxx xxxx 0000 0000 0000 0000 Count... 0000 0000 0000 0000 0000 0000 0000 0000 Count ...
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... Ordering Information Table 43.Ordering Information Ordering Code CY7C67200-48BAXI 48FBGA CY7C67200-BAXIT 48FBGA, Tape and reel CY3663 Development Kit Package Diagram 48-Ball (7. 7. 1.2 mm) FBGA BA48 TOP VIEW PIN 1 CORNER (LASER MARK 7.00±0.10 SEATING PLANE C 2 Purchase of I C™ components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the ...
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... Document History Page Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller Document Number: 38-08014 Issue REV. ECN NO. Date ** 111872 03/22/02 *A 116988 08/23/02 *B 124954 04/10/03 *C 126211 05/23/03 *D 127334 05/29/03 *E 129394 10/07/03 *F 472875 See ECN *G 567317 See ECN KKVTMP Added the lead free information on the Ordering Information Section. Imple- Document #: 38-08014 Rev ...