COM20019I-DZD SMSC, COM20019I-DZD Datasheet
COM20019I-DZD
Specifications of COM20019I-DZD
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COM20019I-DZD Summary of contents
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... Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID COM20019ILJP for 28 pin PLCC package; COM20019I-DZD for 28 pin PLCC lead-free RoHS Compliant package COM20019I-HD for 48 pin TQFP package; COM20019I-HT for 48 pin TQFP lead-free RoHS Compliant package SMSC COM20019I COM20019I Cost Competitive ARCNET (ANSI 878 ...
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... OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 2 DATASHEET SMSC COM20019I ...
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... Transmit Sequence .............................................................................................................................37 6.4.3 Receive Sequence ..............................................................................................................................38 6.5 COMMAND CHAINING..............................................................................................................................39 6.5.1 Transmit Command Chaining .............................................................................................................40 6.5.2 Receive Command Chaining ..............................................................................................................40 6.6 RESET DETAILS .......................................................................................................................................41 6.6.1 Internal Reset Logic ............................................................................................................................41 6.7 INITIALIZATION SEQUENCE ....................................................................................................................41 6.7.1 Bus Determination...............................................................................................................................41 6.8 IMPROVED DIAGNOSTICS ......................................................................................................................42 6.8.1 Normal Results:...................................................................................................................................43 SMSC COM20019I Page 3 DATASHEET Rev. 09-25-07 ...
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... Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................16 Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE...................................17 Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................18 Figure 5.4 - COM20019I NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS...........................................20 Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................21 Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................35 Figure 6 ...
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... ARCNET protocol engine. The flexible microcontroller and media interfaces, eight- page message support, and extended temperature range of the COM20019I make it the only true network controller optimized for use in industrial, embedded, and automotive applications. Using an ARCNET protocol engine is the ideal solution for embedded control applications because it provides a deterministic token- passing protocol, a highly reliable and proven networking scheme, and a data rate 312 ...
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... AD0 14 XTAL2 5 13 XTAL1 PACKAGE TYPE Plastic, LJP = PLCC TEMP RANGE: (Blank) = Commercial: 0°C to +70° Industrial: -40°C to +85°C DEVICE TYPE: 20019 = Universal Local Area Network Controller (with RAM) Page 6 DATASHEET nPULSE 1 17 XTAL2 16 XTAL1 15 VDD 14 VSS 13 N SMSC COM20019I ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS SMSC COM20019I COM20019I 48 PIN TQFP Page 7 DATASHEET 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 RXIN 27 N/C 26 BUSTMG 25 nPULSE2 Rev. 09-25-07 ...
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... On an 80XX-like bus, nWR is an active low signal issued by the microcontroller to indicate a write operation. In this case, a logic "0" on this pin, when the COM20019I is accessed, enables data from the data bus to be written to the device. nRESET Input ...
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... The COM20019I does not support the Normal Mode. Use only in the Backplane Mode. RXIN Input. This signal carries the receive data information from the line transceiver ...
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... Packet Pass the Token CRC No OK? Increment Y N Activity NID for 597.6 us? LENGTH OK? DID =0? N DID =ID? Y SEND ACK Figure 3.1 - COM20019I OPERATION Page 10 DATASHEET Activity for 656 uS Set NID=ID N Broadcast Enabled? Start Timer: Y T=(255-ID 1.168 mS Activity Y On Line? ...
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... TO TRANSMIT, destroy the token and keep any other node from assuming control of the line. When any COM20019I senses an idle line for greater than 656μS, which occurs only when the token Is lost, each COM20019I starts an internal timeout equal to 1.168mS times the quantity 255 minus its own ID ...
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... S timeout expires, the COM20019I releases control of the line. RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20019I on the network will finally have saved a NID value equal to the ID of the COM20019I that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM This 656 μS is equal to the Response Time of 597.6 μS plus the time it takes the COM20019I to start retransmitting another message (usually another INVITATION TO TRANSMIT). 4.5.3 Reconfiguration Time If any node does not receive the token within the Reconfiguration Time, the node will initiate a NETWORK RECONFIGURATION ...
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... A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM DID DID COUNT data ALERT BURST ACK ALERT BURST NAK Page 14 DATASHEET data CRC CRC SMSC COM20019I ...
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... COM20019I. The signal on the A0 pin during the odd location access tells the COM20019I the type of bus. Since multiplexed operation requires active low, activity on the A0 line tells the COM20019I that the bus is non- multiplexed. The device defaults to multiplexed operation. Both determinations may be made simultaneously by performing a WRITE followed by a READ operation to an odd location within the COM20019I Address space 20020D registers ...
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... GND nINTR Differential Driver Configuration * XTAL1 XTAL2 A0/nMUX MHz XTAL +5V RXIN 100 Ohm nPULSE1 NOTE: COM20019 must be in backplane mode FIGURE B Page 16 DATASHEET 75176B or Equiv. Media Interface may be replaced with Figure +5V 2 Receiver 6 HFD3212-002 7 Transmitter HFE4211-014 3 + Fiber Interface (ST Connectors) SMSC COM20019I ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE SMSC COM20019I COM20019I D0-D7 A0/nMU RXIN A1 A2/BAL TXEN nCS nPULSE nRESE nPULSE nRD/nD GND nWR/nDI nINTR ...
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... High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20019I. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive. But the High Speed CPU bus timing doesn't adhere to these timings ...
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... It issues a 1.6µS negative pulse to transmit a logic "1". Note that when used in the open-drain mode, the COM20019I does not have a fail/safe input on the RXIN pin. The nPULSE1 signal actually contains a weak pull-up resistor. This pull-up should not take the place of the resistor required on the media for open drain mode ...
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... COM20019I. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 1.6µS negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20019I is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. ...
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... ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY Figure 5.5 SMSC COM20019I RAM MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR NODE ID RECONFIGURATION LOGIC TIMER - INTERNAL BLOCK DIAGRAM Page 21 DATASHEET ADDITIONAL REGISTERS nPULSE1 ...
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... Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Table 5.1 - Typical Media NOMINAL ATTENUATION PER 1000 FT. IMPEDANCE 93Ω 75Ω 75Ω 150Ω 100Ω 105Ω Page 22 DATASHEET AT 5 MHZ 5.5dB 7.0dB 5.5dB 7.0dB 17.9dB 16.0dB SMSC COM20019I ...
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... The COM20019I derives a 625 kHz and a 312.5 kHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20019I. The 625 kHz clock is the rate at which the program counter operates, while the 312 ...
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... Interrupt Mask Register (IMR) The COM20019I is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic " ...
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... Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20019I does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node ...
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... SUBAD0 and SUBAD1 point to the selection in Register 7. 6.2.11 Sub-Address Register The sub-address register is new to the COM20019I, previously a reserved register. Bits 2, 1 and 0 are used to select one of the registers assigned to address 7h. SUBAD1 and SUBAD0 already exist in the Configuration register on the COM20020B. They are exactly same as those in the Sub-Address register. If the SUBAD1 and SUBAD0 bits in the Configuration register are changed, the SUBAD1and SUBAD0 in the Sub-Address register are also changed ...
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... MHz crystal. The RBUSTMG bit is used to Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20019I ( the timing is the same as in the COM20020 Rev. B). See Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization ...
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... Enquiry. This bit is cleared upon the "POR Clear Flags" command. Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. Refer to the Improved Diagnostics section for further detail. Page 28 DATASHEET SMSC COM20019I ...
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... Available) status bit to logic "1" when the COM20019I next receives the token. This command will cancel any pending receive command. If the COM20019I is not yet receiving a packet, the RI (Receiver Inhibited) bit will be set to logic "1" the next time the token is received. If packet reception is already underway, reception will run to its normal conclusion ...
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... If "c" logic "0", the device handles only short packets. This command resets certain status bits of the COM20019I. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit ...
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... Table 6.9 - Configuration Register SYMBOL DESCRIPTION RESET A software reset of the COM20019I is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. This bit must be brought back to logic " ...
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... Note that ACKs are only sent for packets received with a destination ID equal to the COM20019I's programmed node ID. This feature can be used to put the COM20019I in a 'listen-only' mode, where the transmitter is disabled and the COM20019I is not passing tokens. Defaults low. ...
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... These bits are undefined. EF This bit is used to enable the new enhanced functions in the COM20019I Disable (Default Enable the timing and function is the same as in the COM20020, Revision B. See appendix “A”. EF bit must be ‘1’ if the data rate is over 5Mbps. ...
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... Data Register I/O Address 04H D0-D7 Address Pointer Register I/O Address 02H High 11-Bit Counter Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Memory Data Bus 8 I/O Address 03H Low Memory Address Bus 11 Page 34 DATASHEET INTERNAL RAM SMSC COM20019I ...
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... INTERNAL RAM The integration of the RAM in the COM20019I represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM ...
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... Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20019I does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time ...
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... The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20019I puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...
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... These situations can be determined by either using the improved diagnostic features of the COM20019I or using another software timeout which is greater than the worst case time for a round trip token pass, which occurs when all nodes transmit a maximum length message. ...
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... RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20019I sets the RI bit to logic "1" to signal the microcontroller that the reception is complete. ...
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... Transmit Command Chaining When the processor issues the first "Enable Transmit to Page fnn" command, the COM20019I responds in the usual manner by resetting the TA and TMA bits to prepare for the transmission from the specified page. The TA bit can be used to see if there is currently a transmission pending, but the TA bit is really meant to be used in the non-chaining mode only ...
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... Register will again be updated with the results of the second reception and a second interrupt resulting from the second reception will occur. In the COM20019I, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a " ...
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... Tentative ID. To determine the next logical node, the software should read the Next ID Register. 6.8 IMPROVED DIAGNOSTICS The COM20019I allows the user to better manage the operation of the network through the use of the internal Diagnostic Status Register. A high level on the My Reconfiguration (MYRECON) bit indicates that the Token Reception Timer of this node expired, causing a reconfiguration by this node ...
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... If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20019I contains an internal resistor. The crystal must have an accuracy of 0.020% or better. The oscillation frequency range is from 10 MHz to 20 MHz. ...
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... The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 44 DATASHEET SMSC COM20019I ...
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... Low Input Voltage 1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, and RXIN) High Input Voltage 1 (All inputs except A2, XTAL1, nRESET, nRD, nWR, and RXIN) Low Input Voltage 2 (XTAL1) High Input Voltage 2 (XTAL1) SMSC COM20019I COM20019II SYMBOL MIN TYP MAX V 0.8 IL1 V 2.0 IH1 V 1 ...
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... Schmitt Trigger, All Values =4mA SINK V I =-2mA SOURCE I =-200µA SOURCE V I =16mA SINK V I =-12mA SOURCE V I =24mA SINK V I =-10mA SOURCE V I =48mA SINK Open Drain Driver mA 312.5 Kbps All Outputs Open µA V =0.0V IN µA V < V < SMSC COM20019I ...
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... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20019I = 1MHz 0V MIN TYP MAX C 5.0 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID DATA VALID t1 t2 t12 t11 t6 t13 t5 t9 MUST BE: RBUSTMG bit = 0 Parameter 4T if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 48 DATASHEET t7 t14 Note 2 t8 t10 min max units ARB SMSC COM20019I ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I VALID DATA VALID t1 t2 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID DATA VALID t1 t2 t12 t5 t6 t13 t9 Parameter min Next )** * 4T ARB SLOW ARB = 0 opr from the trailing edge of nDS to the leading edge of the ARB from the trailing edge of nDS to ARB Page 50 DATASHEET t7 Note 2 t8** t8 t14 t10 max units SMSC COM20019I ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I VALID VALID DATA t1 t2 ...
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... VALID DATA CASE 1: RBUSTMG bit = 0 min Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 52 DATASHEET Note 2 t7 max units 5 ARB nS 40 SMSC COM20019I ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I VALID t1 t3 Note 3 t5 ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 CASE 1: RBUSTMG bit = 0 Parameter if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nDS to ARB Page 54 DATASHEET t11 Note 2 t9 VALID DATA min max units 5 ARB SMSC COM20019I ...
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... COM20019 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I VALID t10 ...
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... Note 3 t8 t10 t6 VALID DATA min Next )** 4T ARB 30*** SLOW ARB = 0 opr from the trailing edge of nWR to the leading edge ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 56 DATASHEET Note 2 t5** t7 max units SMSC COM20019I ...
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... Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.10 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I VALID t3 t5 t10 t8 VALID DATA ...
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... Rev. 09-25-07 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM t10 t12 t11 Parameter Page 58 DATASHEET t13 t8 LAST BIT (3200 nS BIT TIME) min typ max units - 1600* nS 3200 800* nS 800* nS 1600 -25 5500 5700 nS 3900 4100 nS 10 1600* nS 3200 SMSC COM20019I ...
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... High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 312.5 Kbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD Figure 8.13 - RESET AND INTERRUPT TIMING SMSC COM20019I t2 1.0V min -200 t2 min ...
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... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM PIN 28L .160-.180 A .090-.120 .013-.021 .026-.032 B 1 .020-.045 C D .485-.495 .450-.456 .390-.430 D 3 .300 .050 BSC F .042-.056 G .042-.048 J .000-.020 R .025-.045 Page 60 DATASHEET SMSC COM20019I ...
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... E1 6.90 H 0. 0.50 Basic θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20019I MAX ~ 1.6 0.10 0.15 1.40 1.45 9.00 9.20 1 4.50 4. Span Measure from Centerline 2 7.00 7.10 9.00 9.10 1 4.50 4. Span Measure from Centerline 2 7.00 7 ...
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... RAM initialization sequence to be written. The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20019I will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 96uS. These values are read as part of the diagnostic test ...
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... CKP3-1 with Pre-Scalar’s internal clocks. C) Shorten The Write Interval Time To The Command Register The COM20019I limits the write interval time for continuous writing to the Command register. The minimum interval time is changed by the Data Rate. It's 800 nS at the 312.5 Kbps and 1.6 μ the 156.25 Kbps. This 1.6 μ ...
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... Tentative-ID register is written, the effect of the old Tentative-ID remains active for a while, which results in an incorrect network map. It can be avoided by a carefully coded software routine, but this requires the programmer to have deep knowledge of how the COM20019I works. Duplicate-ID is mainly used for generating the Network MAP. This has the same issue as Tentative-ID. ...
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... SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS SMSC COM20019I LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer Page 65 ...