LTC4269CDKD-2#PBF Linear Technology, LTC4269CDKD-2#PBF Datasheet - Page 17

• Manufacturer Part Number: LTC4269CDKD-2#PBF
• Description: IC PD/SYNC FORWARD CTRLR 32-DFN
• Manufacturer: Linear Technology
• Type: Power Over Ethernet (PoE)r

Specifications of LTC4269CDKD-2#PBF

• Applications: Power Interface Switch for Power Over Ethernet (PoE) Devices
• Voltage - Supply: 14 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Current - Supply: 1.35mA
• Interface: IEEE 802.3af
• Controller Type: Powered Device Interface Controller (PD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

applicaTions inForMaTion
continues to power the PD load as long as the port volt-
age does not fall below the UVLO threshold. When the
LTC4269-2 port voltage falls below the UVLO threshold,
the PD is disconnected, and classification mode resumes.
C1 discharges through the LTC4269-2 circuitry.
COMPLEMENTARY POWER GOOD
When LTC4269-2 fully charges the load capacitor (C1),
power good is declared and the LTC4269-2 load can safely
begin operation. The LTC4269-2 provides complementary
power good signals that remain active during normal
operation and are deasserted when the port voltage falls
below the PoE UVLO threshold, when the voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown. See Figure 6.
The PWRGD pin features an open-collector output refer-
enced to V
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to V
14V clamp limits the PWRGD pin voltage. Connecting
the PWRGD pin to the SD_V
converter from commencing operation before the PDI
interface completely charges the reservoir capacitor, C1.
The active low PWRGD pin connects to an internal, open-
drain MOSFET referenced to V
directly to the shutdown pin of a DC/DC converter product.
PSE
Figure 5. LTC4269-2 Undervoltage and Overvoltage Lockout
TO
V
LTC4269-2
NEG
PORTN
V
0V TO ON*
>ON*
<UVLO*
>OVLO
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD 36.1V
UVLO THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
PORTP
UNDERVOLTAGE
which can interface directly with the SD_V
OVERVOLTAGE
LOCKOUT
CIRCUIT
– V
PORTN
POWER MOSFET
LTC4269-2
OFF
OFF
OFF
ON
SEC
PORTN
V
pin prevents the DC/DC
PORTP
V
NEG
and can interface
NEG
MIN
CURRENT-LIMITED
TURN ON
5µF
C1
. An internal
+
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LOAD
PD
SEC
When power good is declared and active, the PWRGD pin
is low impedance with respect to V
PWRGD PIN WHEN SHDN IS INVOKED
In PD applications where an auxiliary power supply invokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the “RUN” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
OVERVOLTAGE LOCKOUT
The LTC4269-2 includes an Overvoltage Lockout (OVLO)
feature (Figure 5) which protects the LTC4269-2 and its
load from an overvoltage event. If the input voltage ex-
ceeds the OVLO threshold, the LTC4269-2 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
Figure 6. LTC4269-2 Power Good Functional and State Diagram
V
V
PORTN
PORTN
5
6
LTC4269-2
OVLO
UVLO
TSD
ON
BOLD LINE INDICATES HIGH CURRENT PATH
POWER
GOOD
NOT
AND NOT IN THERMAL SHUTDOWN
CONTROL
CIRCUIT
OR THERMAL SHUTDOWN
ON < V
INRUSH COMPLETE
V
V
PORTP
PORTP
PORTP
< UVLO
> OVLO
< OVLO
POWER
GOOD
PORTN
LTC4269-2
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.
29
28
27
26
PWRGD
PWRGD
V
V
NEG
NEG

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