KSZ8873FLLI Micrel Inc, KSZ8873FLLI Datasheet
KSZ8873FLLI
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KSZ8873FLLI Summary of contents
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... Functional Diagram LinkMD is a registered trademark of Micrel, Inc Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( August 2010 KSZ8873MLL/FLL/RLL ...
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Micrel, Inc. Features • Advanced Switch Features – IEEE 802.1q VLAN support for groups (full-range of VLAN IDs) – VLAN ID tag/untag options, per port basis – IEEE 802.1p/q tag insertion or removal on a per port ...
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... Micrel, Inc. Ordering Information Part Number Temperature Range KSZ8873MLL KSZ8873MLLI –40ºC to +85ºC KSZ8873MLL AM -40 KSZ8873FLL KSZ8873FLLI –40ºC to +85ºC KSZ8873RLL KSZ8873RLLI –40ºC to +85ºC Revision History Revision Date Summary of Changes 1.0 03/25/08 Initial release 1.1 06/26/09 Combined Register Description to initial release. ...
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Micrel, Inc. Contents Pin Description and I/O Assignment ................................................................................................................................. 11 Pin Configuration ................................................................................................................................................................ 16 Functional Description ....................................................................................................................................................... 17 Functional Overview: Physical Layer Transceiver .......................................................................................................... 17 100BASE-TX Transmit ..................................................................................................................................................... 17 100BASE-TX Receive ...................................................................................................................................................... 17 PLL Clock Synthesizer...................................................................................................................................................... 17 Scrambler/De-scrambler (100BASE-TX Only) ...
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Micrel, Inc. Spanning Tree Support..................................................................................................................................................... 34 Rapid Spanning Tree Support .......................................................................................................................................... 35 Tail Tagging Mode ............................................................................................................................................................ 35 IGMP Support ................................................................................................................................................................... 36 IGMP Snooping ......................................................................................................................................................... 36 Multicast Address Insertion in the Static MAC Table ................................................................................................ 36 Port Mirroring Support ...................................................................................................................................................... 36 ...
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Micrel, Inc. Register 32 (0x20): Port 2 Control 0.......................................................................................................................... 56 Register 48 (0x30): Port 3 Control 0.......................................................................................................................... 56 Register 17 (0x11): Port 1 Control 1.......................................................................................................................... 57 Register 33 (0x21): Port 2 Control 1.......................................................................................................................... 57 Register 49 (0x31): Port 3 Control ...
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Micrel, Inc. Register 104 (0x68): TOS Priority Control Register 8 ............................................................................................... 68 Register 105 (0x69): TOS Priority Control Register 9 ............................................................................................... 69 Register 106 (0x6A): TOS Priority Control Register 10............................................................................................. 69 Register 107 (0x6B): TOS Priority Control Register 11............................................................................................. 69 ...
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Micrel, Inc. Register 179 (0xB3): TXQ Split for Q3 in Port 2........................................................................................................ 76 Register 180 (0xB4): TXQ Split for Q2 in Port 2........................................................................................................ 76 Register 181 (0xB5): TXQ Split for Q1 in Port 2........................................................................................................ 77 Register 182 (0xB6): TXQ Split ...
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Micrel, Inc. List of Figures Figure 1. Typical Straight Cable Connection ....................................................................................................................... 19 Figure 2. Typical Crossover Cable Connection ................................................................................................................... 20 Figure 3. Auto-Negotiation and Parallel Operation .............................................................................................................. 21 Figure 4. Destination Address Lookup Flow Chart, Stage 1................................................................................................ 25 Figure ...
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Micrel, Inc. List of Tables Table 1. FX Signal Threshold............................................................................................................................................... 18 Table 2. MDI/MDI-X Pin Definitions ..................................................................................................................................... 18 Table 3. Internal Function Block Status ................................................................................................................................ 23 Table 4. MII Signals ............................................................................................................................................................. 28 Table 5. RMII Clock Setting .................................................................................................................................................. 29 Table ...
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Micrel, Inc. Pin Description and I/O Assignment Pin Number Pin Name 1 RXM1 2 RXP1 3 AGND 4 TXM1 5 TXP1 6 VDDA_3.3 7 AGND 8 ISET 9 VDDA_1.8 10 RXM2 11 RXP2 12 AGND 13 TXM2 14 TXP2 15 ...
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Micrel, Inc. Pin Number Pin Name 28 SMRXDV3 29 SMRXD33/ REFCLKO_3 30 SMRXD32 31 SMRXD31 32 GND 33 SMRXD30 34 SCRS3 SCOL3 SMRXC3 GND 38 VDDC 39 SPIQ 40 SPISN September 2010 (1) Type ...
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Micrel, Inc. Pin Number Pin Name 41 INTRN 42 SCL_MDC 43 SDA_MDIO P1ANEN 46 P1SPD 47 P1DPX 48 GND 49 VDDC 50 P1FFC 51 P3SPD VDDIO 55 GND 56 VDDCO 57 NC ...
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Micrel, Inc. Pin Number Pin Name 59 P1LED0 60 P2LED1 September 2010 (1) Type Description Ipd/O Port 1 LED Indicators: Default: Link/Act. (refer to register 195 bit[5:4]) Strap option: Port 3 duplex mode selection(P3DPX port 3 default to ...
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Micrel, Inc. Pin Number Pin Name 61 P2LED0 62 RSTN 63 FXSD1 64 VDDA_1.8 Notes: 1. Speed : Low (100BASE-TX), High (10BASE-T) Full duplex : Low (full duplex), High (half duplex) Act : Toggle (transmit / receive activity) Link : ...
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Micrel, Inc. Pin Configuration September 2010 64-Pin LQFP (Top View) 16 KSZ8873MLL/FLL/RLL M9999-092309-1.2 ...
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Micrel, Inc. Functional Description The KSZ8873MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8873MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design managed ...
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Micrel, Inc. 100BASE-FX Signal Detection In 100BASE-FX operation, FXSD (fiber signal detect), input pin 15 and 63, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit ...
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Micrel, Inc. Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, ...
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Micrel, Inc. Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...
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Micrel, Inc. Auto-Negotiation The KSZ8873MLL/FLL/RLL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto- negotiation, link partners ...
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Micrel, Inc. ® LinkMD Cable Diagnostics KSZ8873MLL/FLL/RLL supports the LinkMD the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the ...
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Micrel, Inc. KSZ8873MLL/FLL/RLL Function Blocks Normal Mode Internal PLL Clock Enabled Tx/Rx PHY Enabled MAC Enabled Host Interface Enabled Normal Operation Mode This is the default setting bit[1:0]=00 in register 195 after the chip power-up or hardware reset . When ...
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Micrel, Inc. Hardware Power Down KSZ8873 supports a hardware power down mode. When the pin PWRDN is actived low, the entire chip is powered down. Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and ...
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Micrel, Inc. PTF1= NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Figure 4. Destination Address Lookup Flow Chart, Stage 1 September 2010 Start NO VLAN ID Valid? YES FOUND Search Static Table ...
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Micrel, Inc. Spanning Tree IGMP Process Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KSZ8873MLL/FLL/RLL will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size ...
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Micrel, Inc. Switching Engine The KSZ8873MLL/FLL/RLL features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has ...
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Micrel, Inc. To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following: 1. Aggressive back-off (register 3 (0x03), bit [0 excessive collision drop (register 4 (0x04), bit [3]) ...
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Micrel, Inc. The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid ...
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Micrel, Inc. Direction RMII (with respect Signal Name to the PHY) REF_CLK Input CRS_DV Output RXD1 Output RXD0 Output TX_EN Input TXD1 Input TXD0 Input RX_ER Output --- --- The KSZ8873RLL filters error frames, and thus does not implement the ...
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Micrel, Inc. MII Management (MIIM) Interface The KSZ8873MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8873MLL/FLL/RLL. An external ...
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Micrel, Inc. Registers are 8 data bits wide. For read operation, data bits [15:8] are read back as 0’s. For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’. SMI register ...
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Micrel, Inc. QoS Priority Support The KSZ8873MLL/FLL/RLL provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offering four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is ...
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Micrel, Inc. DiffServ-Based Priority DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to determine packet priority ...
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Micrel, Inc. Rapid Spanning Tree Support There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP: Discarding ports do not participate in the active topology and do not learn MAC addresses. Discarding state: ...
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Micrel, Inc. Ingress to Port 3 (Host -> KSZ8873MLL/FLL/RLL) Bit [1,0] 0,0 0,1 1,0 1,1 Bit [3,2] 0,0 0,1 1,0 1,1 Egress from Port 3 (KSZ8873MLL/FLL/RLL->Host) Bit [ IGMP Support For Internet Group Management Protocol (IGMP) support in ...
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Micrel, Inc. Multiple ports can be selected as “receive sniff” or “transmit sniff”. In addition, any port can be selected as the “sniffer port”. All these per port features can be selected through registers 17, 33 and 49 for ports ...
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Micrel, Inc. RST_N SCL SDA The following is a sample procedure for programming the KSZ8873MLL/FLL/RLL with a pre-configured EEPROM: 1. Connect the KSZ8873MLL/FLL/RLL to the EEPROM by joining the SCL and SDA signals of the respective devices Enable ...
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Micrel, Inc. SPI Slave Serial Bus Configuration In managed mode, the KSZ8873MLL/FLL/RLL can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8873MLL/FLL/RLL’s 198 registers. Programming access ...
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Micrel, Inc. SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID SPIQ September 2010 ...
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Micrel, Inc. SPIS_N SPIC SPID X 0 SPIQ SPIS_N SPIC SPID X X SPIQ D7 D6 September 2010 READ COMMAND READ ADDRESS ...
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Micrel, Inc. Loopback Support The KSZ8873MLL/FLL/RLL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end (Remote) ...
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Micrel, Inc. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8873MLL/FLL/RLL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, ...
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Micrel, Inc. MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I also be used to access some of these registers. The latter three interfaces use a different ...
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Micrel, Inc. PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control Bit Name R/W 15 Soft reset RO 14 Loopback R/W 13 Force 100 R/W ...
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Micrel, Inc. PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status Bit Name R capable RO 14 100 Full RO capable 13 100 ...
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Micrel, Inc. PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO ...
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Micrel, Inc. PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): Not supported PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status Bit Name R/W 15 Vct_enable R/W (SC) 14-13 Vct_result RO 12 Vct 10M Short RO 11-9 ...
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Micrel, Inc. Memory Map (8-bit Registers) Global Registers Register (Decimal) Register (Hex) 0-1 0x00-0x01 2-15 0x02-0x0F Port Registers Register (Decimal) Register (Hex) 16-29 0x10-0x1D 30-31 0x1E-0x1F 32-45 0x20-0x2D 46-47 0x2E-0x2F 48-57 0x30-0x39 58-62 0x3A-0x3E 63 0x3F 64-95 0x40-0x5F Advanced Control ...
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Micrel, Inc. Register Description Global Registers (Registers 0 – 15) Register 0 (0x00): Chip ID0 Bit Name R/W 7-0 Family ID RO Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W 7-4 Chip ID RO 3-1 Revision ID ...
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Micrel, Inc. Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass All R/W Frames 6 Port 3 Tail Tag R/W Mode Enable 5 IEEE 802.3x R/W Transmit Direction Flow Control Enable 4 IEEE 802.3x R/W Receive Direction Flow ...
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Micrel, Inc. Bit Name R/W 2 Huge Packet R/W Support 1 Legal R/W Maximum Packet Size Check Enable 0 Reserved R/W Register 5 (0x05): Global Control 3 Bit Name R/W 7 802.1Q VLAN R/W Enable 6 IGMP Snoop R/W Enable ...
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Micrel, Inc. Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved RO 6 Switch MII Half R/W Duplex Mode 5 Switch MII R/W Flow Control Enable 4 Switch MII R/W 10BT 3 Null VID R/W Replacement 2-0 Broadcast ...
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Micrel, Inc. Register 8 (0x08): Global Control 6 Bit Name R/W 7-0 Factory RO Testing Register 9 (0x09): Global Control 7 Bit Name R/W 7-0 Factory RO Testing Register 10 (0x0A): Global Control 8 Bit Name R/W 7-0 Factory RO ...
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Micrel, Inc. Register 14 (0x0E): Global Control 12 Bit Name R/W Description 7 Unknown R/W Send packets with unknown destination MAC addresses to specified port(s) in bits [2:0] of this register. Packet Default =0, Disable Port =1, Enable Enable 6 ...
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Micrel, Inc. Port Registers (Registers 16 – 95) The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port ...
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Micrel, Inc. Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W Description 7 Sniffer Port R/W =1, Port is designated as sniffer port and will ...
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Micrel, Inc. Bit Name R/W 3 Back R/W Pressure Enable 2 Transmit R/W Enable 1 Receive R/W Enable 0 Learning R/W Disable Note: Bits [2:0] are used for spanning tree support. Register 19 (0x13): Port 1 Control 3 Register 35 ...
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Micrel, Inc. Bit Name R/W 5 Self-address R/W filtering enable MACA2 (not for 0x35) 4 Drop Ingress R/W Tagged Frame 3-2 Limit Mode R/W 1 Count IFG R/W 0 Count Pre R/W Register 22[6:0] (0x16): Port 1 Q0 ingress data ...
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Micrel, Inc. Register 23[6:0] (0x17): Port 1 Q1 ingress data rate limit Register 39[6:0] (0x27): Port 2 Q1 ingress data rate limit Register 55[6:0] (0x37): Port 3 Q1 ingress data rate limit Bit Name R/W 7 Reserved R/W 6-0 Q1 ...
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Micrel, Inc. Data Rate Limit for ingress or egress 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 Kbps 512 Kbps 576 Kbps 640 Kbps 704 Kbps 768 Kbps 832 Kbps 896 Kbps 960 Kbps September ...
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Micrel, Inc. Register 26 (0x1A): Port 1 PHY Special Control/Status Register 42 (0x2A): Port 2 PHY Special Control/Status Register 58 (0x3A): Reserved, not applied to port 3 Bit Name R/W 7 Vct 10M Short RO 6-5 Vct_result RO 4 Vct_en ...
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Micrel, Inc. Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 Bit Name R/W 7 Auto R/W Negotiation Enable 6 Force Speed R/W 5 Force Duplex ...
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Micrel, Inc. Bit Name R/W 4 Disable Far- R/W end Fault 3 Power Down R/W 2 Disable Auto R/W MDI/MDI-X 1 Force MDI R/W 0 Loopback R/W Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status ...
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Micrel, Inc. Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W 7 Hp_mdix R/W 6 Reserved RO 5 Polrvs RO 4 Transmit Flow RO Control ...
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Micrel, Inc. Advanced Control Registers (Registers 96-198) The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit DSCP (Differentiated Services Code Point) register set that is used to determine priority from the ToS (Type of Service) field in the ...
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Micrel, Inc. Register 99 (0x63): TOS Priority Control Register 3 Bit Name R/W 7-6 DSCP[31:30] R/W 5-4 DSCP[29:28] R/W 3-2 DSCP[27:26] R/W 1-0 DSCP[25:24] R/W Register 100 (0x64): TOS Priority Control Register 4 Bit Name R/W 7-6 DSCP[39:38] R/W 5-4 ...
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Micrel, Inc. Register 102 (0x66): TOS Priority Control Register 6 Bit Name R/W 7-6 DSCP[55:54] R/W 5-4 DSCP[53:52] R/W 3-2 DSCP[51:50] R/W 1-0 DSCP[49:48] R/W Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-6 DSCP[63:62] R/W 5-4 ...
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Micrel, Inc. Register 105 (0x69): TOS Priority Control Register 9 Bit Name R/W 7-6 DSCP[79:78] R/W 5-4 DSCP[77:76] R/W 3-2 DSCP[75:74] R/W 1-0 DSCP[73:72] R/W Register 106 (0x6A): TOS Priority Control Register 10 Bit Name R/W 7-6 DSCP[87:86] R/W 5-4 ...
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Micrel, Inc. Register 108 (0x6C): TOS Priority Control Register 12 Bit Name R/W 7-6 DSCP[103:102] R/W 5-4 DSCP[101:100] R/W 3-2 DSCP[99:98] R/W 1-0 DSCP[97:96] R/W Register 109 (0x6D): TOS Priority Control Register 13 Bit Name R/W 7-6 DSCP[111:110] R/W 5-4 ...
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Micrel, Inc. Register 111 (0x6F): TOS Priority Control Register 15 Bit Name R/W 7-6 DSCP[127:126] R/W 5-4 DSCP[125:124] R/W 3-2 DSCP[123:122] R/W 1-0 DSCP[121:120] R/W Registers 112 to 117 Registers 112 to 117 contain the switch engine’s MAC address. This ...
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Micrel, Inc. Registers 118 to 120 Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8873 and the external processor. ...
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Micrel, Inc. Register 125 (0x7D): Indirect Data Register 6 Bit Name R/W 7-0 Indirect Data R/W [55:48] Register 126 (0x7E): Indirect Data Register 5 Bit Name R/W 7-0 Indirect Data R/W [47:40] Register 127 (0x7F): Indirect Data Register 4 Bit ...
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Micrel, Inc. Register 154[6:0] (0x9A): Port 1 Q0 Egress data rate limit Register 158[6:0] (0x9E): Port 2 Q0 Egress data rate limit Register 162[6:0] (0xA2): Port 3 Q0 Egress data rate limit Bit Name R/W 7 Egress Rate R/W Limit ...
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Micrel, Inc. Register 166 (0xA6): KSZ8873 mode indicator Bit Name RO 7-0 KSZ8873 RO Mode Indicator Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3 Bit Name RW 7-0 Reserved RO Register 168 (0xA8): High Priority Packet Buffer Reserved ...
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Micrel, Inc. Register 174 (0xAE): PM Usage Flow Control Select Mode 4 Bit Name R/W 7-4 Reserved RO 3-0 Reserved RO Register 175 (0xAF): TXQ Split for Q3 in Port 1 Bit Name R/W 7 Reserved RO 6:0 Reserved RO ...
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Micrel, Inc. Register 181 (0xB5): TXQ Split for Q1 in Port 2 Bit Name R/W 7 Reserved RO 6:0 Reserved RO Register 182 (0xB6): TXQ Split for Q0 in Port 2 Bit Name R/W 7 Reserved RO 6:0 Reserved RO ...
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Micrel, Inc. Register 188 (0xBC): Link Change Interrupt Bit Name R Link R/W Change (LC) Interrupt 6-3 Reserved R Link R/W Change (LC) Interrupt 1 P2 Link R/W Change (LC) Interrupt 0 P1 MII ...
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Micrel, Inc. Register 194 (0xC2): Insert SRC PVID Bit Name R/W 7-6 Reserved RO 5 Insert SRC R/W port 1 PVID at Port 2 4 Insert SRC R/W port 1 PVID at Port 3 3 Insert SRC R/W port 2 ...
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Micrel, Inc. Register 196(0xC4): Sleep Mode Bit Name R/W 7-0 Sleep Mode R/W Register 198 (0xC6): Forward Invalid VID Frame and Host Mode Bit Name R/W 7 Reserved RO 6-4 Forward Invid R/W VID Frame 3 P3 RMII Clock R/W ...
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Micrel, Inc. Static MAC Address Table The KSZ8873 supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KSZ8873 searches both tables to make a packet forwarding decision. In response ...
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Micrel, Inc. 2. Static Address Table Write (Write the 8 Write to reg. 124 (0x7C), static table bits [57:56] Write to reg. 125 (0x7D), static table bits [55:48] Write to reg. 126 (0x7E), static table bits [47:40] Write to reg. ...
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Micrel, Inc. VLAN Table The KSZ8873 uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with ...
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Micrel, Inc. Dynamic MAC Address Table The KSZ8873 maintains the dynamic MAC address table. Read access is allowed only. Bit Name 71 Data Not Ready 70-67 Reserved 66 MAC Empty 65- Valid Entries 55-54 Time Stamp 53-52 Source ...
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Micrel, Inc. MIB (Management Information Base) Counters The KSZ8873 provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped ...
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Micrel, Inc. Offset Counter Name 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets Bit Name 30-16 Reserved ...
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Micrel, Inc. “All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in the following table: Offset Counter Name 0x100 Port1 TX Drop Packets 0x101 Port2 TX Drop Packets 0x102 ...
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Micrel, Inc. Absolute Maximum Ratings Supply Voltage (V _1.8, V )....................................... –0.5V to 2.4V DDA DDC (V _3.3V ................................... –0.5V to 4.0V DDA DDIO Input Voltage ................................................. –0.5V to 4.0V Output Voltage .............................................. –0.5V to 4.0V Lead Temperature ...
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Micrel, Inc. Symbol Parameter T /T Rise/Fall Time r f Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot Output Jitter 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Output Jitter ...
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Micrel, Inc. Timing Specifications EEPROM Timing Symbols t cyc1 ov1 September 2010 Figure 16. EEPROM Interface Input Timing Diagram Figure 17. EEPROM Interface Output Timing Diagram Parameters Clock cycle Setup time Hold time Output valid ...
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Micrel, Inc. MII Timing Figure 18. MAC Mode MII Timing – Data Received from MII Figure 19. MAC Mode MII Timing – Data Transmitted to MII September 2010 10Base-T/100Base-TX Symbol Parameter Min Typ Clock 400/40 t Cycle CYC3 Set-Up 4 ...
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Micrel, Inc. September 2010 Figure 20. PHY Mode MII Timing – Data Received from MII Figure 21. PHY Mode MII Timing – Data Transmitted to MII 10BaseT/100BaseT Symbol Parameter Min Clock Cycle t CYC4 Set-Up Time Hold ...
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Micrel, Inc. RMII Timing eceive Tim ing ...
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Micrel, Inc Slave Mode Timing September 2010 Figure 24. I2C Input Timing Figure 25. I2C Start Bit Timing Figure 26. I2C Stop Bit Timing I2C Output Timing Figure 27. 94 KSZ8873MLL/FLL/RLL M9999-092309-1.2 ...
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Micrel, Inc. Symbols Parameters t Clock cycle CYC t Setup time S t Hold time H t Start bit setup time TBS t Start bit hold time TBH t Stop bit setup time SBS t Stop bit hold time SBH ...
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Micrel, Inc. SPI Timing Symbols CHSL t SLCH t CHSH t SHCH t SHSL t DVCH t CHDX t CLCH t CHCL t DLDH t DHDL September 2010 Figure 28. SPI Input Timing Parameters Clock frequency SPISN ...
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Micrel, Inc. Symbols CLQX t CLQV QLQH t QHQL t SHQZ September 2010 Figure 29. SPI Output Timing Parameters Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time ...
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Micrel, Inc. Auto-Negotiation Timing A u to-N egotiation - F ast lse Symbols Parameters t FLP burst to FLP ...
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Micrel, Inc. MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising ...
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Micrel, Inc. Reset Timing The KSZ8873MLL/FLL/RLL reset timing requirement is summarized in the following figure and table. Symbols Parameters Stable supply voltages to reset High t sr Configuration setup time Configuration hold time ch Reset to strap-in ...
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Micrel, Inc. Reset Circuit The reset circuit in Figure is recommended for powering up the KSZ8873MLL/FLL/RLL if reset is triggered only by the power supply. The reset circuit in Figure 34 is recommended for applications where reset is driven by ...
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Micrel, Inc. Selection of Isolation Transformers An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...
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Micrel, Inc. Package Information September 2010 103 KSZ8873MLL/FLL/RLL M9999-092309-1.2 ...
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Micrel, Inc. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in ...