LTC4269CDKD-1#TRPBF Linear Technology, LTC4269CDKD-1#TRPBF Datasheet - Page 19

IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#TRPBF

Manufacturer Part Number
LTC4269CDKD-1#TRPBF
Description
IC PD/OPTO FLYBACK CTRLR 32-DFN
Manufacturer
Linear Technology
Type
Power Over Ethernet (PoE)r
Datasheet

Specifications of LTC4269CDKD-1#TRPBF

Applications
Power Interface Switch for Power Over Ethernet (PoE) Devices
Voltage - Supply
14 V ~ 16 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-DFN
Current - Supply
1.35mA
Interface
IEEE 802.3af
Controller Type
Powered Device Interface Controller (PD)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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APPLICATIONS INFORMATION
Transient Voltage Suppressor
The LTC4269-1 specifi es an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-1, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4269-1 as
shown in Figure 7.
Classifi cation Resistor (R
The R
corresponding to the PD power classifi cation. Select the
value of R
between the R
4, or fl oat the R
rent is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classifi cation circuit.
Load Capacitor
The IEEE 802.3af/at specifi cation requires that the PD
maintains a minimum load capacitance of 5μF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
This occurs when the PSE voltage drops quickly. The input
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
The load capacitor can store signifi cant energy when fully
charged. The PD design must ensure that this energy is not
inadvertently dissipated in the LTC4269-1. For example,
if the V
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
CLASS
PORTP
CLASS
resistor sets the classifi cation load current,
CLASS
pin shorts to V
CLASS
from Table 2 and connect the resistor
and V
pin if the classifi cation load cur-
PORTN
CLASS
PORTN
)
pins as shown in Figure
while the capacitor
T2P Interface
When a 2-event classifi cation sequence successfully
completes, the LTC4269-1 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-1 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an opto-isolator to communicate across the
DC/DC converter isolation barrier. The pull-up resistor R
is sized according to the requirements of the opto-isola-
tor operating current, the pull-down capability of the T2P
pin, and the choice of V
the PoE supply rail (which the LTC4269-1 V
to), or from the voltage source that supplies power to
the DC/DC converter. Option 1 has the advantage of not
drawing power unless T2P is declared active.
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
PSE
PSE
TO
TO
–54V
–54V
Figure 8. T2P Interface Examples
V
V
PORTN
PORTN
LTC4269-1
LTC4269-1
V
V
+
PORTP
PORTP
V
. V
T2P
T2P
NEG
+
for example can come from
V
V
+
+
LTC4269-1
R
R
P
P
PORTP
TO PD LOAD
TO PD LOAD
19
42691 F08
is tied
42691fb
P

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