LTC4269CDKD-1#TRPBF Linear Technology, LTC4269CDKD-1#TRPBF Datasheet - Page 30

• Manufacturer Part Number: LTC4269CDKD-1#TRPBF
• Description: IC PD/OPTO FLYBACK CTRLR 32-DFN
• Manufacturer: Linear Technology
• Type: Power Over Ethernet (PoE)r

Specifications of LTC4269CDKD-1#TRPBF

• Applications: Power Interface Switch for Power Over Ethernet (PoE) Devices
• Voltage - Supply: 14 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Current - Supply: 1.35mA
• Interface: IEEE 802.3af
• Controller Type: Powered Device Interface Controller (PD)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC4269-1
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
between the primary-side switch and secondary-side syn-
chronous switch(es) and the subsequent current spike in
the transformer. This spike will cause additional component
stress and a loss in regulator effi ciency.
The primary gate delay resistor is set with the following
equation:
A good starting point is 15k.
Soft-Start Function
The LTC4269-1 contains an optional soft-start function that
is enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
The SFST node is discharged to 0.8V when a fault occurs.
A fault occurs when V
current sense voltage is greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
30
R
t
SS
PGDLY
=
C
SFST
( )
kΩ
20µA
CMP
• 1.4V
=
t
PGDLY
pin from exceeding that on the SFST
CC
CMP
= 70kΩ • C
is too low (undervoltage lockout),
9.01
( )
node voltage is also pulled low
ns
+ 47
SFST
( )
µF
Switcher’s UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
Referring to Figure 13, the voltage hysteresis at V
equal to the change in bias current times R
procedure is to select the desired V
hysteresis, V
where:
R
V
(13a) UV Turning On
IN
B
R
R
I
R
R
Figure 13. UVLO Pin Function and Recommended Filtering
A
B
UVLO
is then selected with the desired turn-on voltage:
B
A
=
UVLO
=
LTC4969-1
⎛
⎝ ⎜
= I
V
I
V
UVHYS
V
UVLO
UVLOL
IN(ON)
I
UVLO
UVLO
UVHYS
R
A
– I
– 1
. Then:
IN
V
(13b) UV Turning Off
UVLOH
IN
⎞
⎠ ⎟
. The gate drivers are disabled when
R
R
A
B
UVLO
is approximately 3.4μA
LTC4969-1
I
UVLO
IN
referred voltage
(13c) UV Filtering
A
C
. The design
UVLO
V
IN
R
R
R
42691 F13
A1
A2
B
42691fb
IN
UVLO
is