LTC4269CDKD-1#TRPBF Linear Technology, LTC4269CDKD-1#TRPBF Datasheet - Page 5

IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#TRPBF

Manufacturer Part Number
LTC4269CDKD-1#TRPBF
Description
IC PD/OPTO FLYBACK CTRLR 32-DFN
Manufacturer
Linear Technology
Type
Power Over Ethernet (PoE)r
Datasheet

Specifications of LTC4269CDKD-1#TRPBF

Applications
Power Interface Switch for Power Over Ethernet (PoE) Devices
Voltage - Supply
14 V ~ 16 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-DFN
Current - Supply
1.35mA
Interface
IEEE 802.3af
Controller Type
Powered Device Interface Controller (PD)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
respect to V
Note 4: All voltages are with respect to V
Note 5: Input voltage specifi cations are defi ned with respect to LTC4269-1
pins and meet IEEE 802.3af/at specifi cations when the input diode bridge
is included.
Note 6: Signature resistance is measured via the ΔV/ΔI method with the
minimum ΔV of 1V. The LTC4269-1 signature resistance accounts for the
additional series resistance in the input diode bridge.
PARAMETER
Load Compensation
Load Compensation to V
Feedback Pin Load Compensation Current
UVLO Function
UVLO Pin Threshold (V
UVLO Pin Bias Current
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifi cations are at T
NEG
. V
CC
has internal 19.5V clamp with respect to GND.
UVLO
SENSE
)
Offset Voltage
PORTN
pin unless otherwise noted.
CONDITIONS
V
V
V
V
RCMP
SENSE
UVLO
UVLO
= 1.2V
= 1.3V
+
with V
= 20mV, V
A
= 25°C.
SENSE
The
FB
+
= 0V
= 1.230V
l
denotes the specifi cations which apply over the full operating
Note 7: An invalid signature after the 1st classifi cation event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current defi ned as
1.237/R
Note 9: This parameter is assured by design and wafer level testing.
Note 10: V
R
voltages are with respect to GND.
Note 11: Supply current does not include gate charge current to the
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
tON
= 90k, R
CLASS
CC
= 14V; PG, SG Open; V
PGDLY
and does not include variations in R
= 27.4k, R
ENDLY
1.215
–0.25
–4.50
= 90k, unless otherwise specifi ed. All
CMP
MIN
= 1.5V, V
1.240
LTC4269-1
–3.4
TYP
20
1
0
SENSE
CLASS
resistance.
= 0V, R
1.265
–2.50
MAX
0.25
CMP
= 1k,
42691fb
UNITS
5
mV
μA
μA
μA
V

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