LTC4269CDKD-1#PBF Linear Technology, LTC4269CDKD-1#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC4269CDKD-1#PBF
• Description: IC PD/OPTO FLYBACK CTRLR 32-DFN
• Manufacturer: Linear Technology
• Type: Power Over Ethernet (PoE)r

Specifications of LTC4269CDKD-1#PBF

• Applications: Power Interface Switch for Power Over Ethernet (PoE) Devices
• Voltage - Supply: 14 V ~ 16 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-DFN
• Current - Supply: 1.35mA
• Interface: IEEE 802.3af
• Controller Type: Powered Device Interface Controller (PD)
• Input Voltage: 60V
• Supply Current: 6.4mA
• Digital Ic Case Style: DFN
• No. Of Pins: 32
• Duty Cycle (%): 88%
• Frequency: 100kHz
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 32
• Mounting: Surface Mount
• Package Type: DFN EP
• Case Length: 7mm
• Screening Level: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN FUNCTIONS
LTC4269-1
10
the V
start is complete. The ramp time is approximately 70ms
per μF of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an
external capacitor (C
oscillator frequency. The frequency is approximately
100kHz • 100/C
FB (Pin 16): Feedback Amplifi er Input. Feedback is usually
sensed via a third winding and enabled during the fl yback
period. This pin also sinks additional current to compensate
for load current variation as set by the R
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
V
is used for frequency compensation of the switcher con-
trol loop. It is the output of the feedback amplifi er and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifi er output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from V
upon V
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from V
undervoltage lockout supersedes this function, so V
must be great enough to start the part.
The bias current on this pin has hysteresis such that the
bias current is sourced when UVLO threshold is exceeded.
This introduces a hysteresis at the pin equivalent to the bias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
pin to V
Information section for details. This pin is used for the
UVLO function of the switching regulator. The PD interface
section has an internal UVLO.
SENSE
These pins are used to measure primary-side switch cur-
rent through an external sense resistor. Peak primary-side
CMP
CMP
(Pin 17): Frequency Compensation Control. V
PORTP
PORTP
–
CC
, SENSE
voltage and thus limits peak current until soft-
if not using this function. See the Applications
to this pin sets an undervoltage lockout based
level (not V
OSC
+
(Pins 19, 20): Current Sense Inputs.
(pF).
OSC
CC
) to GND, defi nes the controller
). When the UVLO pin is below
CMP
pin. Keep the
CC
. The V
CMP
CC
CC
current is used in the converter control loop. Make Kelvin
connections to the sense resistor R
problems. SENSE
current (V
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
C
Connect a capacitor from C
the effects of parasitic resistances in the feedback sensing
path. A 0.1μF ceramic capacitor suffi ces for most applica-
tions. Short this pin to GND when load compensation is
not needed.
R
Connect a resistor from R
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (R
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic cur-
rents fl ow during voltage transitions. See the Applications
Information section for details.
V
to V
Pin 27 must be electrically tied together at the package.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedence signals power-up completion. PWRGD
is referenced to V
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain. Low impedance signals power-up completion.
PWRGD is referenced to V
V
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connection for both signal ground and gate driver grounds
of the fl yback controller. This pin should be connected to
V
CMP
NEG
PORTP
NEG
CMP
PORTN
.
(Pins 26, 27): System Negative Rail. Connects V
(Pin 21): Load Compensation Capacitive Control.
(Pin 22): Load Compensation Resistive Control.
(Pin 32): Positive Power Input. Tie to the input
CMP
through an internal power MOSFET. Pin 26 and
at its maximum voltage) SENSE pins have
–
NEG
connects to the GND side. At maximum
and features a 14V clamp.
PORTN
CMP
CMP
to GND in order to reduce
to GND in order to com-
.
PGDLY
SENSE
) to set delay from
to reduce noise
42691fb
NEG