IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 


Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
1
2
3
4
5
6
7
8
9
10
11
Page 11
12
Page 12
13
Page 13
14
Page 14
15
Page 15
16
Page 16
17
Page 17
18
Page 18
19
Page 19
20
Page 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Page 15/44

Download datasheet (387Kb)Embed
PrevNext
APPLICATIONS INFORMATION
50
40
1st CLASS
30
2nd CLASS
ON
20
10
DETECTION V1
1st MARK 2nd MARK
DETECTION V2
INRUSH
1st CLASS
2nd CLASS
40mA
DETECTION V1
1st MARK 2nd MARK
DETECTION V2
50
dV
INRUSH
=
dt
C1
40
30
OFF
ON
20
10
–10
–20
–30
–40
–50
INRUSH = 100mA
R
= 30.9Ω
CLASS
V
PORTN
I
=
LOAD
R
LOAD
LTC4269-1
I
IN
R
V
CLASS
PORTP
PSE
R
CLASS
T2P
V
V
PORTN
NEG
, T2P and PD Current
Figure 4. V
NEG
as a Result of 2-Event Classifi cation
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receive a false indication of a 2-event classifi cation if a PSE
OFF
port is pre-charged to a voltage above the detection voltage
range before the fi rst detection cycle. The IEEE working
group modifi ed the standard to prevent this possibility by
requiring a Type 2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
LOAD, I
LOAD
The LTC4269-1 conforms to this standard by corrupting
the signature resistance. This also discharges the port
before the PSE begins the next detection cycle.
TIME
PD STABILITY DURING CLASSIFICATION
Classifi cation presents a challenging stability problem due
to the wide range of possible classifi cation load current.
The onset of the classifi cation load current introduces a
voltage drop across the cable and increases the forward
OFF
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classifi cation with the
= R
C1
LOAD
onset and removal of the classifi cation load current.
TIME
The LTC4269-1 prevents this oscillation by introducing a
voltage hysteresis window between the detection and clas-
TIME
sifi cation ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classifi cation load current, thus providing a trouble-free
transition between detection and classifi cation modes.
TRACKS
V
PORTN
The LTC4269-1 also maintains a positive I-V slope through-
out the classifi cation range up to the on-voltage. In the
event a PSE overshoots beyond the classifi cation voltage
range, the available load current aids in returning the PD
back into the classifi cation voltage range. (The PD input
R
may otherwise be “trapped” by a reverse-biased diode
LOAD
bridge and the voltage held by the 0.1μF capacitor).
C1
INRUSH CURRENT
42691 F04
Once the PSE detects and optionally classifi es the PD,
the PSE then applies powers on the PD. When the
LTC4269-1 input voltage rises above the on-voltage
threshold, LTC4269-1 connects V
the internal power MOSFET.
LTC4269-1
to V
through
NEG
PORTN
42691fb
15