IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 

Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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LTC4269-1
APPLICATIONS INFORMATION
The LTC4269-1 has an internal clamp on V
mately 19.5V. This provides some protection for the part
in the event that the switcher is off (UVLO low) and the
V
node is pulled high. If R
is sized correctly, the part
CC
TR
should never attain this clamp voltage.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifi er (V
pin) to ground as shown in Figure 15.
CMP
Because of the sampling behavior of the feedback amplifi er,
compensation is different from traditional current mode
controllers. Normally only C
is required. R
VCMP
be used to add a zero, but the phase margin improvement
traditionally offered by this extra resistor is usually already
accomplished by the nonzero secondary circuit impedance.
C
can be used to add an additional high frequency
VCMP2
pole and is usually sized at 0.1 times C
V
CMP
17
C
R
VCMP2
42691 F15
Figure 15. V
Compensation Network
CMP
In further contrast to traditional current mode switchers,
V
pin ripple is generally not an issue with the LTC4269-1.
CMP
The dynamic nature of the clamped feedback amplifi er
forms an effective track/hold type response, whereby the
V
voltage changes during the fl yback pulse, but is then
CMP
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the V
during the current comparator sense action (current mode
switching).
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
32
of approxi-
Slope Compensation
CC
The LTC4269-1 incorporates current slope compensation.
Slope compensation is required to ensure current loop
stability when the DC is greater than 50%. In some switching
regulators, slope compensation reduces the maximum peak
current at higher duty cycles. The LTC4269-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
Minimum Load Considerations
At light loads, the LTC4269-1 derived regulator goes into
can
VCMP
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
t
resistor. If this produces more power than the
ON(MIN)
load requires, power will fl ow back into the primary dur-
ing the off period when the synchronization switch is on.
.
VCMP
This does not produce any inherently adverse problems,
although light load effi ciency is reduced.
Maximum Load Considerations
VCMP
The current mode control uses the V
C
VCMP
and amplifi ed sense resistor voltage as inputs to the
current comparator. When the amplifi ed sense voltage
exceeds the V
is turned off.
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
reaches its 2.56V clamp. At clamp, the primary-side
CMP
MOSFET will turn off at the rated 100mV V
repeats on the next cycle.
It is possible for the peak primary switch currents as
voltage stable
referred across R
CMP
because of the minimum switch on time blanking. If the
voltage on V
turn-on time, the SFST capacitor is discharged, causing
the discharge of the V
the peak current on the next cycle and will reduce overall
stress in the primary switch.
node voltage
CMP
node voltage, the primary-side switch
CMP
level. This
SENSE
to exceed the max 100mV rating
SENSE
exceeds 205mV after the minimum
SENSE
capacitor. This then reduces
CMP
42691fb