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LTC4269CDKD1#PBF
LTC4269CDKD1#PBF  

Manufacturer Part Number  LTC4269CDKD1#PBF 
Description  IC PD/OPTO FLYBACK CTRLR 32DFN 
Manufacturer  Linear Technology 
Type  Power Over Ethernet (PoE) 
LTC4269CDKD1#PBF datasheet 

Specifications of LTC4269CDKD1#PBF  

Applications  Power Interface Switch for Power Over Ethernet (PoE) Devices  Voltage  Supply  14 V ~ 16 V 
Operating Temperature  0°C ~ 70°C  Mounting Type  Surface Mount 
Package / Case  32DFN  Current  Supply  1.35mA 
Interface  IEEE 802.3af  Controller Type  Powered Device Interface Controller (PD) 
Input Voltage  60V  Supply Current  6.4mA 
Digital Ic Case Style  DFN  No. Of Pins  32 
Duty Cycle (%)  88%  Frequency  100kHz 
Operating Temperature Range  0Â°C To +70Â°C  Msl  MSL 1  Unlimited 
Rohs Compliant  Yes  Operating Temperature (max)  70C 
Operating Temperature (min)  0C  Pin Count  32 
Mounting  Surface Mount  Package Type  DFN EP 
Case Length  7mm  Screening Level  Commercial 
Lead Free Status / RoHS Status  Lead free / RoHS Compliant 
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APPLICATIONS INFORMATION
ShortCircuit Conditions
Loss of current limit is possible under certain conditions
such as an output shortcircuit. If the duty cycle exhibited
by the minimum ontime is greater than the ratio of
secondary winding voltage (referredtoprimary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cyclebycycle to some
higher level. Expressed mathematically, the requirement
to maintain shortcircuit control is
(
I
• R
SC
= t
<
DC
• f
MIN
ON(MIN)
OSC
where:
t
is the primaryside switch minimum ontime
ON(MIN)
I
is the shortcircuit output current
SC
N
is the secondarytoprimary turns ratio (N
SP
(other variables as previously deﬁ ned)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for shortcircuit protection
and adds any additional circuitry to prevent destruction.
Output Voltage Error Sources
The LTC42691’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
• The internal bandgap voltage reference sets the reference
voltage for the feedback ampliﬁ er. The speciﬁ cations
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondarytofeedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current ﬂ ows through the
impedances of the winding resistance, synchronous
MOSFET R
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s offtime. So, divide the load current by
(1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC42691 load compensation circuitry
)
+ R
(see Load Compensation). If multiple output windings are
SEC
DS(ON)
used, the ﬂ yback winding will have a signal that represents
V
• N
IN
SP
an amalgamation of all these windings impedances. Take
care that you examine worstcase loading conditions when
tweaking the voltages.
Power MOSFET Selection
/N
)
SEC
PRI
The power MOSFETs are selected primarily on the criteria of
onresistance R
breakdown voltage (BV
and maximum drain current (ID
For the primaryside power MOSFET, the peak current is:
I
PK(PRI)
where XMIN is peaktopeak current ratio as deﬁ ned
earlier.
For each secondaryside power MOSFET, the peak cur
rent is:
I
PK(SEC)
Select a primaryside power MOSFET with a BVDSS
greater than:
≥I
BV
DSS
where NSP reﬂ ects the turns ratio of that secondaryto
primary winding. LLKG is the primaryside leakage induc
tance and CP is the primaryside capacitance (mostly from
the drain capacitance (COSS) of the primaryside power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
LTC42691
and output capacitor ESR. The DC
DS(ON)
, input capacitance, draintosource
DS(ON)
), maximum gate voltage (V
DSS
).
(MAX)
P
⎛
X
⎞
IN
MIN
=
• 1+
⎝ ⎜
⎠ ⎟
V
• DC
2
IN(MIN)
MAX
I
⎛
X
⎞
OUT
MIN
=
• 1+
⎝ ⎜
⎠ ⎟
1− DC
2
MAX
V
L
OUT(MAX)
LKG
+ V
+
PK
IN(MAX)
C
N
P
SP
)
GS
42691fb
33