IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 


Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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APPLICATIONS INFORMATION
Short-Circuit Conditions
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
(
I
• R
SC
= t
<
DC
• f
MIN
ON(MIN)
OSC
where:
t
is the primary-side switch minimum on-time
ON(MIN)
I
is the short-circuit output current
SC
N
is the secondary-to-primary turns ratio (N
SP
(other variables as previously defi ned)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switch on time. Additionally, several real world effects such
as transformer leakage inductance, AC winding losses and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
Output Voltage Error Sources
The LTC4269-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
• The internal bandgap voltage reference sets the reference
voltage for the feedback amplifi er. The specifi cations
detail its variation.
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
• The transformer secondary current fl ows through the
impedances of the winding resistance, synchronous
MOSFET R
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s off-time. So, divide the load current by
(1 – DC).
If the output load current is relatively constant, the feedback
resistive divider is used to compensate for these losses.
Otherwise, use the LTC4269-1 load compensation circuitry
)
+ R
(see Load Compensation). If multiple output windings are
SEC
DS(ON)
used, the fl yback winding will have a signal that represents
V
• N
IN
SP
an amalgamation of all these windings impedances. Take
care that you examine worst-case loading conditions when
tweaking the voltages.
Power MOSFET Selection
/N
)
SEC
PRI
The power MOSFETs are selected primarily on the criteria of
on-resistance R
breakdown voltage (BV
and maximum drain current (ID
For the primary-side power MOSFET, the peak current is:
I
PK(PRI)
where XMIN is peak-to-peak current ratio as defi ned
earlier.
For each secondary-side power MOSFET, the peak cur-
rent is:
I
PK(SEC)
Select a primary-side power MOSFET with a BVDSS
greater than:
≥I
BV
DSS
where NSP refl ects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage induc-
tance and CP is the primary-side capacitance (mostly from
the drain capacitance (COSS) of the primary-side power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
LTC4269-1
and output capacitor ESR. The DC
DS(ON)
, input capacitance, drain-to-source
DS(ON)
), maximum gate voltage (V
DSS
).
(MAX)
P
X
IN
MIN
=
• 1+
⎝ ⎜
⎠ ⎟
V
• DC
2
IN(MIN)
MAX
I
X
OUT
MIN
=
• 1+
⎝ ⎜
⎠ ⎟
1− DC
2
MAX
V
L
OUT(MAX)
LKG
+ V
+
PK
IN(MAX)
C
N
P
SP
)
GS
42691fb
33