IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 

Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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LTC4269-1
APPLICATIONS INFORMATION
The other 1% is due to the bulk C component, so use:
I
OUT
C
OUT
1% • V
• f
OUT
OSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfi es the required bulk C.
Continuing our example, the output capacitor needs:
(
5V • 1− 49.4%
≤ 1% •
ESR
COUT
5.3A
5.3A
= 600µF
C
OUT
1% • 5 • 200kHz
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
One way to reduce cost and improve output ripple is to use a
simple LC fi lter. Figure 18 shows an example of the fi lter.
L1, 0.1μH
+
+
FROM
C1
C
OUT
SECONDARY
47μF
470μF
WINDING
3
Figure 18.
The design of the fi lter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
1/4 the size of the nonfi lter
OUT
solution. Make C1 1/4 of C
to make the second fi lter
OUT
pole independent of C
. C1 may be best implemented
OUT
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1μH fi lter inductor is suffi cient. Add a small ceramic
capacitor (C
) for high frequency noise on V
OUT2
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
Circuit simulation is a way to optimize output capacitance
and fi lters, just make sure to include the component
parasitic. LTC SwitcherCAD
TM
is a terrifi c free circuit
simulation tool that is available at www.linear.com. Final
36
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
signifi cantly impact ripple. Refer to the PC Board Layout
section for more details.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4269-1 is specifi ed to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
)
can routinely see peak voltages in excess of 10kV. To
= 4mΩ
protect the LTC4269-1, it is highly recommended that the
SMAJ58A unidirectional 58V transient voltage suppressor
be installed between the diode bridge and the LTC4269-1
(D3 in Figure 2).
ISOLATION
The 802.3 standard requires Ethernet ports to be electrically
isolated from all other conductors that are user accessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
V
OUT
common methods to meet the isolation requirement. If
C
OUT2
R
LOAD
there will be any user accessible connection to the PD,
1μF
then an isolated DC/DC converter is necessary to meet
42691 F18
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electrical connections to the LTC4269-1 or support circuitry
other than the RJ-45 port.
LAYOUT CONSIDERATIONS FOR THE LTC4269-1
The LTC4269-1’s PD front end is relatively immune to
layout problems. Excessive parasitic capacitance on the
. For
OUT
R
pin should be avoided. Include a PCB heat sink
CLASS
to which the exposed pad on the bottom of the package
can be soldered. This heat sink should be electrically
connected to GND. For optimum thermal performance,
make the heat sink as large as possible. Voltages in a
PD can be as large as 57V for PoE applications, so high
voltage layout techniques should be employed. The SHDN
SwitcherCAD is a trademark of Linear Technology Corporation.
and V
)
PORTN
PORTP
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