IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 

Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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APPLICATIONS INFORMATION
pin should be separated from other high voltage pins, like
V
, V
, to avoid the possibility of leakage currents
PORTP
NEG
shutting down the LTC4269-1. If not used, tie SHDN to
V
. The load capacitor connected between V
PORTN
V
of the LTC4269-1 can store signifi cant energy when
NEG
fully charged. The design of a PD must ensure that this
energy is not inadvertently dissipated in the LTC4269-1.
The polarity-protection diodes prevent an accidental short
on the cable from causing damage. However if, V
is shorted to V
inside the PD while capacitor C1
PORTP
is charged, current will fl ow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4269-1
directly to the ground terminal of the V
capacitor, the bottom terminal of the current sense resistor
and the ground terminal of the input capacitor, using a
ground plane with multiple vias. Place the V
immediately adjacent to the V
and GND pins on the IC
CC
package. This capacitor carries high di/dt MOSFET gate
drive currents. Use a low ESR ceramic capacitor.
Take care in PCB layout to keep the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
also minimizes magnetic fi eld radiation. Figure 19 outlines
the critical paths.
V
CC
C
VCC
V
CC
PG
V
CC
V
CC
SG
Keep electric fi eld radiation low by minimizing the length
and area of traces (keep stray capacitances low). The drain
of the primary-side MOSFET is the worst offender in this
and
category. Always use a ground plane under the switcher
PORTP
circuitry to prevent coupling between PCB planes.
Check that the maximum BV
are not exceeded due to inductive ringing. This is done by
viewing the MOSFET node voltages with an oscilloscope. If
PORTN
it is breaking down, either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
Place the small-signal components away from high frequen-
cy switching nodes. This allows the use of a pseudo-Kelvin
connection for the signal ground, where high di/dt gate
driver currents fl ow out of the IC ground pin in one direction
(to the bottom plate of the V
decoupling
CC
small-signal currents fl ow in the other direction.
Keep the trace from the feedback divider tap to the FB pin
short to preclude inadvertent pick-up.
capacitor
CC
For applications with multiple switching power converters
connected to the same input supply, make sure that the
input fi lter capacitor for the LTC4269-1 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple which could
interfere with the LTC4269-1 operation. A few inches of PC
trace or wire (L ≅ 100nH) between the C
and the actual source V
sharing problems.
T1
V
IN
GATE
TURN-ON
+
C
MP
VIN
GATE
TURN-OFF
R
+
SENSE
C
R
T2
Figure 19. Layout Critical High Current Paths
LTC4269-1
ratings of the MOSFETs
DSS
decoupling capacitor) and
CC
of the LTC4269-1
IN
, is suffi cient to prevent current
IN
OUT
+
C
OUT
GATE
Q4
TURN-ON
MS
GATE
Q3
TURN-OFF
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