IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part NumberLTC4269CDKD-1#PBF
DescriptionIC PD/OPTO FLYBACK CTRLR 32-DFN
ManufacturerLinear Technology
TypePower Over Ethernet (PoE)
LTC4269CDKD-1#PBF datasheet
 


Specifications of LTC4269CDKD-1#PBF

ApplicationsPower Interface Switch for Power Over Ethernet (PoE) DevicesVoltage - Supply14 V ~ 16 V
Operating Temperature0°C ~ 70°CMounting TypeSurface Mount
Package / Case32-DFNCurrent - Supply1.35mA
InterfaceIEEE 802.3afController TypePowered Device Interface Controller (PD)
Input Voltage60VSupply Current6.4mA
Digital Ic Case StyleDFNNo. Of Pins32
Duty Cycle (%)88%Frequency100kHz
Operating Temperature Range0°C To +70°CMslMSL 1 - Unlimited
Rohs CompliantYesOperating Temperature (max)70C
Operating Temperature (min)0CPin Count32
MountingSurface MountPackage TypeDFN EP
Case Length7mmScreening LevelCommercial
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On-Time
vs Temperature
340
R
= 158k
tON(MIN)
330
320
310
300
290
280
270
260
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
42691 G28
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4269-1
operation and corrupt the signature resistance. If unused,
tie SHDN to V
.
PORTN
T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low imped-
ance indicates the presence of a Type 2 PSE.
R
(Pin 3): Class Select Input. Connect a resistor
CLASS
between R
and V
to set the classifi cation load
CLASS
PORTN
current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
V
(Pins 5, 6): Input Voltage, Negative Rail. Pin 5 and
PORTN
Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous rectifi er. Large dynamic currents may fl ow during
voltage transitions. See the Applications Information
section for details.
V
(Pin 10): Supply Voltage Pin. Bypass this pin to
CC
GND with a 4.7μF , or more, capacitor. This pin has a 19.5V
clamp to ground. V
has an undervoltage lockout func-
CC
tion that turns the part on when V
15.3V and off at 9.7V. In a conventional trickle-charge
bootstrapped confi guration, the V
PG Delay Time vs Temperature
300
250
R
= 27.4k
PGDLY
200
150
R
= 16.9k
PGDLY
100
50
0
125
–50
–25
0
25
50
75
TEMPERATURE (°C)
increases signifi cantly during turn-on causing a benign
relaxation oscillation action on the V
not start normally.
t
(Pin 11): Pin for external programming resistor to
ON
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feed-
back method. See the Applications Information section
for details.
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifi er for a fi xed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for fl yback voltage sensing.
See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to
discharge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
is approximately
capacitor (C
CC
primary current through the sense resistor. It is also used
supply current
to control converter inrush at start-up. The SFST clamps
CC
LTC4269-1
Enable Delay Time
vs Temperature
325
R
= 90k
ENDLY
305
285
265
245
225
205
–50
–25
0
25
50
100
125
TEMPERATURE (°C)
42691 G29
pin if the part does
CC
) to GND, controls the ramp-up of peak
SFST
75
100
125
42691 G30
42691fb
9