TDA8034HN/C1,118 NXP Semiconductors, TDA8034HN/C1,118 Datasheet
TDA8034HN/C1,118
Specifications of TDA8034HN/C1,118
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TDA8034HN/C1,118 Summary of contents
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TDA8034HN Smart card interface Rev. 3.0 — 17 January 2011 1. General description The TDA8034HN is a cost-effective analog interface for asynchronous and synchronous smart cards operating 1.8 V. Using few external components, the ...
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... NXP Semiconductors 3. Applications Pay TV Electronic payment Identification Bank card readers 4. Quick reference data Table 1. Quick reference data 3 DDP DD DD(INTF) Symbol Parameter Supply V power supply voltage DDP V supply voltage DD V interface supply voltage DD(INTF) I supply current DD I power supply current DDP I interface supply current ...
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... NXP Semiconductors 5. Ordering information Table 2. Ordering information Type number Package Name TDA8034HN/C1 HVQFN24 6. Block diagram V DD(INTF) R1 PORADJ 18 ( PRESN 3 RSTIN 5 CMDVCCN 19 OFFN 6 LEVEL CLKDIV1 SHIFTER 7 CLKDIV2 2 VCC_SEL2 4 VCC_SEL1 20 I/OUC 21 AUX1UC 22 AUX2UC 1 100 nF V DD(INTF) ALARMN, CLKUP, EN1, PVCC, EN4, EN3, EN2 and CLK are internal signals. ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Pin description Symbol Pin Supply Type DD(INTF) DD(INTF) VCC_SEL2 DD(INTF) RSTIN DD(INTF) VCC_SEL1 DD(INTF) CMDVCCN DD(INTF) CLKDIV1 DD(INTF) CLKDIV2 DD(INTF) PRESN DD(INTF) I I/O CC AUX1 10 V I/O CC AUX2 11 V I/O CC GND ...
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... NXP Semiconductors Table 3. Pin description …continued Symbol Pin Supply Type DDP DDP PORADJ DD(INTF) OFFN DD(INTF) I/OUC 20 V I/O DD(INTF) AUX1UC 21 V I/O DD(INTF) AUX2UC 22 V I/O DD(INTF) XTAL1 XTAL2 [ input output, I/O = input/output ground and P = power supply. [2] If pin PRESN is LOW, the card is considered to be present. During card insertion, debouncing can occur on these signals. To counter this, the TDA8034HN has a built-in debouncing timer (typically 8 ms) ...
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... NXP Semiconductors 8.2 Voltage supervisor Fig 3. The voltage supervisor monitors the voltage of the V providing both Power-On Reset (POR) and supply drop-out detection during a card session. The supervisor threshold voltages for V V DD(INTF) inactive irrespective of the command line levels. After hys sent to a digital controller in order to reset the TDA8034HN. This defined reset pulse of approximately 8 ms, i.e. (t the Shutdown mode during the supply voltage power on ...
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... NXP Semiconductors 8.3 Clock circuits The clock signal from pin CLK to the card is either supplied by an external clock signal connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and XTAL2. The TDA8034HN automatically detects if an external clock is connected to XTAL1, eliminating the need for a separate pin to select the clock source. ...
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... NXP Semiconductors 8.4 Input and output circuits When pins I/O and I/OUC are pulled HIGH using an 11 kΩ resistor between pins I/O and V and/or between pins I/OUC and V CC referenced to V The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables falling edge detection on the other line, making it the slave ...
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... NXP Semiconductors CMDVCCN VCC_SEL1 VCC_SEL2 (internal pin) PRESN Fig 6. 8.7 Activation sequence The following device activation sequence is applied when using an external clock; see Figure 7: 1. Pin CMDVCCN is pulled LOW (t0). 2. The internal oscillator is triggered (t0). 3. The internal oscillator changes to high frequency (t1). ...
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... NXP Semiconductors CMDVCCN XTAL1 V CC I/O CLK RSTIN RST I/OUC OSCINT Fig 7. 8.8 Deactivation sequence When a session ends, the microcontroller sets pin CMDVCCN HIGH. The TDA8034HN then executes an automatic deactivation sequence by counting the sequencer back to the inactive state (see 1. Pin RST is pulled LOW (t11). ...
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... NXP Semiconductors Remark: The value of period times the period interval of the internal oscillator (i.e. ± 25 μs). CMDVCC XTAL1 OSCINT Fig 8. 8.9 V regulator CC The V CC The V CC 120 mA. This detection is internally filtered, enabling spurious current pulses up to 200 mA with a duration of a few milliseconds to be drawn by the card without causing deactivation. However, the average current value must stay below maximum ...
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... NXP Semiconductors • In card sessions, pin CMDVCCN is LOW: when pin OFFN goes LOW, the fault detection circuit triggers the automatic emergency deactivation sequence (see Figure deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN returns to HIGH. This check identifies the fault as either a hardware problem or a card removal incident ...
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... NXP Semiconductors PRESN OFFN CMDVCCN V CC (1) Deactivation caused by card withdrawal. (2) Deactivation caused by short-circuit. Fig 10. Operation of debounce feature with pins OFFN, CMDVCCN, PRESN and V 9. Limiting values Remark: All card contacts are protected against any short-circuit to any other card contact. Stress beyond the levels indicated in the device ...
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... NXP Semiconductors 10. Thermal characteristics Table 6. Thermal characteristics Symbol Package name Parameter R HVQFN24 thermal resistance from junction to ambient th(j-a) 11. Characteristics Table 7. Characteristics of IC supply voltage 3 DDP DD DD(INTF) Symbol Parameter Supply V power supply voltage DDP V supply voltage DD V interface supply voltage pin V DD(INTF) ...
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... NXP Semiconductors Table 7. Characteristics of IC supply voltage 3 DDP DD DD(INTF) Symbol Parameter I output current o V supply voltage CC V peak-to-peak ripple ripple(p-p) voltage I supply current CC SR slew rate Crystal oscillator: pins XTAL1 and XTAL2 C external capacitance ext f crystal frequency xtal f external frequency ext ...
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... NXP Semiconductors Table 7. Characteristics of IC supply voltage 3 DDP DD DD(INTF) Symbol Parameter Data lines to the card: pins I/O, AUX1and AUX2 V output voltage o I output current o V LOW-level output OL voltage V HIGH-level output OH voltage V LOW-level input IL voltage V HIGH-level input IH voltage V hysteresis voltage hys I LOW-level input current pin I/O; V ...
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... NXP Semiconductors Table 7. Characteristics of IC supply voltage 3 DDP DD DD(INTF) Symbol Parameter I LOW-level input current pull-up resistance pu t input rise time r(i) t output rise time r(o) t input fall time f(i) t output fall time f(o) I pull-up current pu Internal oscillator f internal oscillator osc(int) frequency ...
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... NXP Semiconductors Table 7. Characteristics of IC supply voltage 3 DDP DD DD(INTF) Symbol Parameter f frequency on pin CLK CLK δ duty cycle SR slew rate Control inputs: pins CLKDIV1, CLKDIV2, RSTIN, VCC_SEL1 and VCC_SEL2 V LOW-level input IL voltage V HIGH-level input IH voltage V hysteresis voltage hys I LOW-level input current V ...
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... NXP Semiconductors [1] To meet these specifications one 220 nF and one 470 nF. Using decoupling capacitors of one 220 nF ±20 % and one 470 nF ±20 %. [2] [3] Using the integrated 9 kΩ pull-up resistor connected to V [4] Using the integrated 10 kΩ pull-up resistor connected to V [5] The transition time and the duty factor definitions are shown in [6] Pins PRESN and CMDVCCN are active LOW ...
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... NXP Semiconductors 12. Application information V DD(INTF) Fig 12. Application diagram TDA8034HN Product data sheet MICROCONTROLLER V DD(INTF DD(INTF) 1 VCC_SEL2 100 nF 2 RSTIN 3 VCC_SEL1 4 CMDVCCN 5 CLKDIV1 6 CARD CONNECTOR All information provided in this document is subject to legal disclaimers. Rev. 3.0. — 17 January 2011 TDA8034HN Smart card interface ...
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... NXP Semiconductors 13. Package outline HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 14. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 12. Acronym EMV ESD ESR FCDM HBM LDO MM NMOS POR TDA8034HN Product data sheet maximum peak temperature ...
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... NXP Semiconductors 16. Revision history Table 13. Revision history Document ID Release date TDA8034HN v.3.0 20110117 • Modifications: • TDA8034HN v.2.0 20101112 • Modifications: TDA8034HN_1 20100205 TDA8034HN Product data sheet Data sheet status Product data sheet Table 2 “Ordering information”: type number updated into TDA8034HN/C1 Table 3 “ ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 4. Clock configuration . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 6. Thermal characteristics . . . . . . . . . . . . . . . . . .14 Table 7. Characteristics of IC supply voltage . . . . . . . .14 Table 8. Protection characteristics . . . . . . . . . . . . . . . .19 Table 9. Timing characteristics . . . . . . . . . . . . . . . . . . .19 Table 10. SnPb eutectic process (from J-STD-020C .23 Table 11. Lead-free process (from J-STD-020C .23 Table 12 ...
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... NXP Semiconductors 20. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 Fig 3. Voltage supervisor circuit . . . . . . . . . . . . . . . . . . . .6 Fig 4. Voltage supervisor waveforms . . . . . . . . . . . . . . . .6 Fig 5. Basic layout for using an external clock Fig 6. Shutdown and Deep shutdown mode activation/deactivation . . . . . . . . . . . . . . . . . . . . . .9 Fig 7. Activation sequence at t3 .10 Fig 8. Deactivation sequence . . . . . . . . . . . . . . . . . . . . 11 Fig 9. Emergency deactivation sequence after card removal ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 8.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 6 8.3 Clock circuits ...