PCA9665D,112 NXP Semiconductors, PCA9665D,112 Datasheet

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PCA9665D,112

Manufacturer Part Number
PCA9665D,112
Description
IC CNTRLR PARALLEL/I2C 20-SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9665D,112

Controller Type
I²C Bus Controller
Interface
I²C
Voltage - Supply
2.3 V ~ 3.6 V
Current - Supply
100µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935279242112
PCA9665D
PCA9665D
1. General description
2. Features
The PCA9665 serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I
system to communicate bidirectionally with the I
master or a slave and can be a transmitter or receiver. Communication with the I
carried out on a Byte or Buffered mode using interrupt or polled handshake. The
PCA9665 controls all the I
no external timing element required.
The PCA9665 has the same footprint as the PCA9564 with additional features:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PCA9665
Fm+ parallel bus to I
Rev. 03 — 12 August 2008
Parallel-bus to I
Both master and slave functions
Multi-master capability
Internal oscillator trimmed to 15 % accuracy reduces external components
1 Mbit/s and up to 25 mA SCL/SDA I
I
Software reset on parallel bus
68-byte data buffer
Operating supply voltage: 2.3 V to 3.6 V
5 V tolerant I/Os
Standard-mode and Fast-mode I
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: DIP20, SO20, TSSOP20, HVQFN20
1 MHz transmission speeds
Up to 25 mA drive capability on SCL/SDA
68-byte buffer
I
Software reset on the parallel bus
2
2
C-bus General Call capability
C-bus General Call
2
C-bus protocol converter and interface
2
C-bus specific sequences, protocol, arbitration and timing with
2
C-bus controller
2
C-bus capable and compatible with SMBus
OL
(Fast-mode Plus (Fm+)) capability
2
2
C-bus. The PCA9665 can operate as a
C-bus and allows the parallel bus
Product data sheet
2
C-bus is

Related parts for PCA9665D,112

PCA9665D,112 Summary of contents

Page 1

PCA9665 Fm+ parallel bus to I Rev. 03 — 12 August 2008 1. General description The PCA9665 serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I system to communicate bidirectionally with the I master or a ...

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... NXP Semiconductors 3. Applications I Add I I Add additional I I Converts 8 bits of parallel data to serial data stream to prevent having to run a large number of traces across the entire printed-circuit board 4. Ordering information Table 1. Ordering information +85 C. amb Type number Topside mark PCA9665BS 9665 PCA9665D PCA9665D ...

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... NXP Semiconductors 5. Block diagram PCA9665 FILTER SDA SDA CONTROL AA ENSIO STA STO SI FILTER SCL SCL CONTROL ENSIO STA STO SI CLOCK SELECTOR OSCILLATOR Fig 1. Block diagram of PCA9665 PCA9665_3 Product data sheet data BUS BUFFER SD7 SD6 SD5 SD4 68-BYTE I2CDAT – data register – read/write BUFFER – ...

Page 4

... NXP Semiconductors 6. Pinning information 6.1 Pinning i.c. V Fig 2. Fig 4. PCA9665_3 Product data sheet SDA 3 18 SCL 4 17 RESET 5 16 INT PCA9665D 002aab020 Pin configuration of SO20 SDA SCL RESET INT PCA9665N i. 002aab019 Pin configuration of DIP20 Rev. 03 — 12 August 2008 PCA9665 ...

Page 5

... NXP Semiconductors 6.2 Pin description Table 2. Symbol Pin i. INT RESET SCL SDA V DD [1] HVQFN20 package die supply ground is connected to both the and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...

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... NXP Semiconductors 7. Functional description 7.1 General The PCA9665 acts as an interface device between standard high-speed parallel buses and the serial I data transfer between the I byte or buffered basis, using either an interrupt or polled handshake. 7.2 Internal oscillator The PCA9665 contains an internal 28.5 MHz oscillator which is used for all I The oscillator requires up to 550 s to start-up after ENSIO bit is set to ‘ ...

Page 7

... NXP Semiconductors Table 4. Register name I2CCOUNT I2CADR I2CSCLL I2CSCLH I2CTO I2CPRESET I2CMODE Fig 6. PCA9665_3 Product data sheet Indirect register selection by setting and Register function byte count own address SCL LOW period SCL HIGH period time-out parallel software reset 2 I C-bus mode ...

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... NXP Semiconductors 7.3.1 Direct registers 7.3.1.1 The Status register, I2CSTA ( I2CSTA is an 8-bit read-only register. The two least significant bits are always zero. The six most significant bits contain the status code. There are 30 possible status codes. When I2CSTA contains F8h, it indicates the idle state and therefore no serial interrupt is requested. All other I2CSTA values correspond to defi ...

Page 9

... NXP Semiconductors In Byte mode, the CPU can read or write a single byte at a time. In Buffered mode, the CPU can read or write bytes at a time. See more detail. Remark: The I2CDAT register will capture the serial address as data when addressed via the serial bus. ...

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... NXP Semiconductors Table 12. Bit Symbol Description ENSIO PCA9665_3 Product data sheet I2CCON - Control register ( bit description The Assert Acknowledge flag the AA flag is set, an acknowledge (LOW level on SDA) will be returned during the acknowledge clock pulse on the SCL line when: • ‘Own slave address’ has been received (as defined in I2CADR register). ...

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... NXP Semiconductors Table 12. Bit Symbol Description 5 STA 4 STO MODE Remark: ENSIO bit value must be changed only when the I 7.3.1.5 The indirect data field access register, INDIRECT ( The registers in the indirect address space can be accessed using the INDIRECT data field. Before writing or reading such a register, the INDPTR register should be written with the address of the indirect register that needs to be accessed. Once the INDPTR register contains the appropriate value, reads and writes to the INDIRECT data fi ...

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... NXP Semiconductors 7.3.2 Indirect registers 7.3.2.1 The Byte Count register, I2CCOUNT (indirect address 00h) The I2CCOUNT register is an 8-bit read/write register. It contains the number of bytes that have been stored in Master/Slave Buffered Receiver mode, and the number of bytes to be sent in Master/Slave Buffered Transmitter mode. Bit 7 is the last byte control bit and applies to the Master/Slave Buffered Receiver mode only ...

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... NXP Semiconductors 7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h) I2CSCLL and I2CSCLH are 8-bit read/write registers. They define the data rate for the PCA9665 when used as a bus master. The actual frequency is determined by t where SCL is HIGH), t ...

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... NXP Semiconductors 7.3.2.4 The Time-out register, I2CTO (indirect address 04h) I2CTO is an 8-bit read/write register used to determine the maximum time that SCL is allowed LOW logic state before the I PCA9665 initiates a forced action on the I When the I LOW SCL transition. Table 21 Table 22. ...

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... NXP Semiconductors 2 7.3.2.6 The I C-bus mode register, I2CMODE (indirect address 06h) I2CMODE is an 8-bit read/write register. It contains the control bits that select the correct timing parameters when the device is used in master mode (AC[1:0]). Timing parameters involved with AC[1:0] are t Table 23. ...

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... NXP Semiconductors 8. PCA9665 modes 8.1 Configuration modes Byte mode and Buffered mode are selected using the MODE bit in I2CCON register: MODE = 0: Byte mode MODE = 1: Buffered mode 8.1.1 Byte mode The Byte mode allows communication on a single command basis. Only one specific command is executed at a time and the Status Register is updated once this single command has been performed ...

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... NXP Semiconductors P — STOP condition In Figure circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not generated when I2CSTA = F8h. This happens on a STOP condition or when an external reset is generated (at power-up, when RESET pin is going LOW or during a software reset on the parallel bus) ...

Page 18

... NXP Semiconductors • B0h if the PCA9665 lost the arbitration and is addressed as a slave transmitter (slave mode enabled with • 68h if the PCA9665 lost the arbitration and is addressed as a slave receiver (slave mode enabled with • D8h if the PCA9665 lost the arbitration and is addressed as a slave receiver during a ...

Page 19

... NXP Semiconductors successful S transmission to a Slave Receiver 08h next transfer started with a repeated START condition Not Acknowledge received after the slave address Not Acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave from master to slave ...

Page 20

... NXP Semiconductors Table 27. Master Transmitter Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 08h A START condition has been transmitted 10h A repeated START condition has been transmitted 18h SLA+W has been transmitted; ACK has been received 20h SLA+W has been transmitted ...

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... NXP Semiconductors Table 27. Master Transmitter Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 30h Data byte in I2CDAT has been transmitted; NACK has been received 38h Arbitration lost in SLA+W or Data bytes PCA9665_3 Product data sheet …continued Application software response ...

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... NXP Semiconductors 8.3.2 Master Receiver Byte mode In the Master Receiver Byte mode, a number of data bytes are received from a slave transmitter one byte at a time (see Transmitter Byte mode. The Master Receiver Byte mode may now be entered by setting the STA bit. The I state machine will fi ...

Page 23

... NXP Semiconductors successful S SLA reception from a Slave Transmitter 08h next transfer started with a repeated START condition Not Acknowledge received after the slave address arbitration lost in slave address or Acknowledge bit arbitration lost and addressed as slave from master to slave from slave to master any number of data bytes and ...

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... NXP Semiconductors Table 28. Master Receiver Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 08h A START condition has been transmitted 10h A repeated START condition has been transmitted 38h Arbitration lost in NACK bit 40h SLA+R has been transmitted; ACK ...

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... NXP Semiconductors 8.3.3 Slave Receiver Byte mode In the Slave Receiver Byte mode, a number of data bytes are received from a master transmitter one byte at a time (see and I2CCON must be loaded as shown in Table 29. Bit Symbol Value The upper 7 bits are the master the control bit that allows the PCA9665 to respond or not to the General Call address (00h) ...

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... NXP Semiconductors reception of own slave address and one or more data bytes; all are Acknowledged. last data byte received is Not Acknowledged arbitration lost as MST and addressed as slave reception of the General Call address and one or more data bytes last data byte received is Not Acknowledged ...

Page 27

... NXP Semiconductors Table 31. Slave Receiver Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 60h Own SLA+W has been received; ACK has been returned 68h Arbitration lost in SLA+R/W as master; Own SLA+W has been received, ACK has been returned ...

Page 28

... NXP Semiconductors Table 31. Slave Receiver Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 E0h Previously addressed with General Call; Data has been received; ACK has been returned E8h Previously addressed with General Call; Data has been received; ...

Page 29

... NXP Semiconductors 8.3.4 Slave Transmitter Byte mode In the Slave Transmitter Byte mode, a number of data bytes are transmitted to a master receiver one byte at a time (see Receiver Byte mode. When I2CADR and I2CCON have been initialized, the PCA9665 waits until it is addressed by its own slave address followed by the data direction bit which must be ‘ ...

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... NXP Semiconductors Table 32. Slave Transmitter Byte mode (MODE = 0) Status Status of the 2 code I C-bus and the (I2CSTA) PCA9665 A8h Own SLA+R has been received; ACK has been returned B0h Arbitration lost in SLA+R/W as master; Own SLA+R has been received, ACK has been returned ...

Page 31

... NXP Semiconductors 8.4 Buffered mode 8.4.1 Master Transmitter Buffered mode In the Master Transmitter Buffered mode, a number of data bytes are transmitted to a slave receiver several bytes at a time (see Buffered mode can be entered, I2CCON must be initialized as shown in Table 33. Bit Symbol Value Table 34. ...

Page 32

... NXP Semiconductors • 30h if the slave address with direction bit has been successfully sent and no acknowledgement (NACK) has been received while transmitting the data bytes (number of total bytes sent is lower than or equal to value in I2CCOUNT). • 38h if the PCA9665 lost the arbitration when sending the slave address with the direction bit or when sending data bytes. • ...

Page 33

... NXP Semiconductors successful S transmission to a Slave Receiver 08h next transfer started with a repeated START condition Not Acknowledge received after the slave address Not Acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave from master to slave ...

Page 34

Table 35. Master Transmitter Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 08h A START condition Load SLA+W and has been the data bytes transmitted 10h ...

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Table 35. Master Transmitter Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 28h BC[6:0] bytes in Load the data I2CDAT have been bytes or transmitted; ACK ...

Page 36

... NXP Semiconductors 8.4.2 Master Receiver Buffered mode In the Master Receiver Buffered mode, a number of data bytes are received from a slave transmitter several bytes at a time (see Master Transmitter Byte mode. The Master Receiver Buffered mode may now be entered by setting the STA bit. The ...

Page 37

... NXP Semiconductors successful reception S SLA R from a Slave Transmitter 08h next transfer started with a repeated START condition Not Acknowledge received after the slave address arbitration lost in slave address or Acknowledge bit arbitration lost and addressed as slave from master to slave from slave to master any number of data bytes and ...

Page 38

Table 36. Master Receiver Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 08h A START condition Load SLA+R has been transmitted 10h A repeated START Load ...

Page 39

Table 36. Master Receiver Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 50h BC[6:0] data bytes Read data bytes have been received; or ACK has been ...

Page 40

... NXP Semiconductors 8.4.3 Slave Receiver Buffered mode In the Slave Receiver Buffered mode, a number of data bytes are received from a master transmitter several bytes at a time (see mode, I2CADR and I2CCON must be loaded as shown in Table 37. Bit Symbol Value The upper 7 bits are the master ...

Page 41

... NXP Semiconductors If the LB bit is reset (logic 0), the PCA9665 will return an acknowledge for all the bytes that will be received. The maximum number of bytes that are received in a single sequence is defined by BC[6:0] in I2CCOUNT register as shown in If the LB bit is set (logic 1) during a transfer, the PCA9665 will return a not acknowledge (logic 1) on SDA after receiving the last byte ...

Page 42

Table 40. Slave Receiver Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 60h Own SLA+W has No I2CDAT action been received; or ACK has been returned ...

Page 43

Table 40. Slave Receiver Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 80h Previously addressed Read data bytes with own slave or address; BC[6:0] data bytes ...

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Table 40. Slave Receiver Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 E8h Previously addressed Read data bytes with General Call; or BC[6:0] data bytes have ...

Page 45

... NXP Semiconductors 8.4.4 Slave Transmitter Buffered mode In the Slave Transmitter Buffered mode, a number of data bytes are transmitted to a master receiver several bytes at a time (see Slave Receiver Buffered mode. When I2CADR and I2CCON have been initialized, the PCA9665 waits until it is addressed by its own slave address followed by the data direction bit which must be ‘ ...

Page 46

Table 41. Slave Transmitter Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 A8h Own SLA+R has Load data bytes been received; or ACK has been returned ...

Page 47

Table 41. Slave Transmitter Buffered mode (MODE = 1) Status Status of the Application software response 2 code I C-bus and the To/from I2CDAT (I2CSTA) PCA9665 C8h BC[6:0] bytes in No I2CDAT action I2CDAT have been or transmitted (AA = ...

Page 48

... NXP Semiconductors 8.5 Buffered mode examples 8.5.1 Buffered Master Transmitter mode of operation 1. Program the I2CCOUNT register with the number of bytes that need to be sent to the 2 I C-bus (BC[6:0] has a value from 01h to 44h). LB bit is used for Receiver mode only and can be set ...

Page 49

... NXP Semiconductors 3. Program I2CCON register to initiate the Master Receiver Buffered sequence. In Master mode, if STA = 1, a START command is sent. An interrupt will be asserted and the SI bit is set in the I2CCON register after the START has been sent. The I2CSTA register contains the status of the transmission. MODE bit must be set to ‘1’ each time a write to the I2CCON register is performed ...

Page 50

... NXP Semiconductors 6. More sequences (program I2CCOUNT register, load data bytes in I2CDAT buffer, write the I2CCON register to send the data to the I when sequence has been executed) can be performed as long as the master acknowledges the bytes sent by the PCA9665 and Slave Transmitter Buffered mode ends when the I PCA9665 goes to Non-addressed Slave mode ...

Page 51

... NXP Semiconductors – the SCL line is held LOW by the PCA9665 after the 2 bytes have been sent – the PCA9665 sends an Interrupt, sets and updates I2CSTA register – I2CSTA reads 28h 5. Program I2CCOUNT = 40h (64 bytes to read and Last byte acknowledged). 6. Load I2CDAT with A1h (I 7. Program I2CCON with STA = MODE = 1. – ...

Page 52

... NXP Semiconductors In Buffered Receiver mode, when an interrupt is generated and SI is set to 1 (after a STOP command or a buffer full condition), the buffer pointer is reset and points at the first received data byte. Reading the I2CCOUNT register then indicates the number of bytes that have been sent or received (BC[6:0]). Reading of the data from I2CDAT buffer can then be initiated starting with the fi ...

Page 53

... NXP Semiconductors Remark: Request to send or receive a number of bytes equal higher than 68 (BC[6:0] = 000 0000 or BC[6:0] > 100 0100) will cause no data to be transferred and an interrupt to be generated after writing to the I2CCON register. I2CSTA status register is loaded with FCh that indicates that an invalid value was requested to be loaded in I2CCOUNT ...

Page 54

... NXP Semiconductors Table 44. Unbuffered Mode (MODE = 0) Control bits Master Transmitter mode • address/data are transmitted on a byte basis Slave Transmitter mode • NACK returned after own slave address received • switch to not addressed slave mode any time 2 during an I C-bus sequence ...

Page 55

... NXP Semiconductors Table 45. Buffered Mode (MODE = 1) Control bits Master Transmitter mode • address/data are transmitted on a multiple byte basis = BC[6:0] value Slave Transmitter mode • NACK returned after own slave address received • in addressed mode, data are transmitted on a multiple byte basis = BC[6:0] value • ...

Page 56

... NXP Semiconductors Table 45. Buffered Mode (MODE = 1) Control bits Master Transmitter mode • address/data are transmitted on a multiple byte basis = BC[6:0] value Slave Transmitter mode • ACK returned after own slave address received • in addressed mode, data are transmitted on a multiple byte basis = BC[6:0] value • ...

Page 57

... NXP Semiconductors 8.8 Miscellaneous states There are four I2CSTA codes that do not correspond to a defined PCA9665 state (see Table 46). These are discussed in Table 46. Miscellaneous states 2 Status Status of the I C-bus code and the PCA9665 (I2CSTA) F8h On hardware or software reset or STOP 70h Bus error ...

Page 58

... NXP Semiconductors 8.8.4 I2CSTA = 78h This status code indicates that the SCL line is stuck LOW. 8.9 Some special cases The PCA9665 has facilities to handle the following special cases that may occur during a serial transfer. 8.9.1 Simultaneous repeated START conditions from two masters A repeated START condition may be generated in the Master Transmitter or Master Receiver modes ...

Page 59

... NXP Semiconductors STA flag SDA line SCL line Fig 16. Forced access to a busy I 2 8.9.4 I C-bus obstructed by a LOW level on SCL or SDA C-bus hang-up occurs if SDA or SCL is pulled LOW by an uncontrolled source. If the SCL line is obstructed (pulled LOW device on the bus, no further serial transfer is possible, and the PCA9665 cannot resolve this type of problem ...

Page 60

... NXP Semiconductors STA flag SDA line SCL line Fig 17. Recovering from a bus obstruction caused by a LOW level on SDA 8.9.5 Bus error A bus error occurs when a START or STOP condition is present at an illegal position in the format frame. Examples of illegal positions are during the serial transfer of an address byte, a data or an acknowledge bit ...

Page 61

... NXP Semiconductors 8.11 Reset Reset of the PCA9665 to its default state can be performed in 2 different ways: • By holding the RESET pin LOW for a minimum of t • By using the Parallel Software Reset sequence as described in access to INDPTR Indirect Register pointer A[1:0] 00 I2CPRESET register selected ...

Page 62

... NXP Semiconductors LOW: V Fig 19. Schematic to power-on/power-off PCA9665 2 8.12 I C-bus timing diagrams, Unbuffered mode The diagrams PCA9665 in master/slave functions. SCL SDA INT 7-bit address R START condition from slave receiver Master PCA9665 writes data to slave transmitter. Fig 20. Bus timing diagram; Unbuffered Master Transmitter mode ...

Page 63

... NXP Semiconductors SCL SDA INT 7-bit address R START condition from slave Master PCA9665 reads data from slave transmitter. Fig 21. Bus timing diagram; Unbuffered Master Receiver mode SCL SDA INT (1) 7-bit address R START condition from slave PCA9665 External master receiver reads data from PCA9665. ...

Page 64

... NXP Semiconductors 2 8.13 I C-bus timing diagrams, Buffered mode The diagrams PCA9665 in master/slave functions. SCL SDA INT (1) 7-bit address R START condition from slave receiver Master PCA9665 writes data to slave transmitter. (1) 7-bit address + R byte and number of bytes sent = value programmed in I2CCOUNT register (BC[6:0] Fig 24. Bus timing diagram ...

Page 65

... NXP Semiconductors SCL SDA INT (1) 7-bit address R START condition from slave PCA9665 External master receiver reads data from PCA9665. (1) As defined in I2CADR register. (2) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0] Fig 26. Bus timing diagram; Buffered Slave Transmitter mode SCL SDA ...

Page 66

... NXP Semiconductors 9. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 67

... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 31. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...

Page 68

... NXP Semiconductors 10. Application design-in information V DD ALE 80C51 V SS Fig 33. Application diagram using the 80C51 10.1 Specific applications The PCA9665 is a parallel bus to I devices to interface with I not have an integrated C-bus port. The PCA9665 can also be used to add more I devices, provide a higher frequency, lower voltage migration path for the PCF8584 and convert 8 bits of parallel data to a serial bus to avoid running multiple traces across the printed-circuit board ...

Page 69

... NXP Semiconductors Fig 34. Adding I 10.3 Add additional I The PCA9665 can be used to convert 8-bit parallel data into additional multiple master capable I microprocessor, custom ASIC, DSP, etc., already have an I more additional I components that cannot be located on the same bus (e.g., 100 kHz and 400 kHz slaves on different buses so that each bus can operate at its maximum potential) ...

Page 70

... NXP Semiconductors 11. Limiting values Table 47. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I I input current I I output current O P total power dissipation tot P/out power dissipation per output T storage temperature ...

Page 71

... NXP Semiconductors 12. Static characteristics Table 48. Static characteristics +85 C; unless otherwise specified. DD amb Symbol Parameter Supply V supply voltage DD I supply current DD V power-on reset voltage POR Inputs WR, RD, A0, A1, CE, RESET V LOW-level input voltage IL V HIGH-level input voltage IH I leakage current ...

Page 72

... NXP Semiconductors 13. Dynamic characteristics Table 49. Dynamic characteristics (3.3 volt 3 +85 C; unless otherwise specified. (See CC amb Symbol Parameter Initialization timing t power-on initialization time init(po) Serial interface initialization timing t serial interface initialization time init(sintf) RESET timing (see Figure 37) t reset pulse width ...

Page 73

... NXP Semiconductors Table 50. Dynamic characteristics (2.5 volt 2 +85 C; unless otherwise specified. (See CC amb Symbol Parameter Initialization timing t power-on initialization time init(po) Serial interface initialization timing t serial interface initialization time init(sintf) RESET timing (see Figure 37) t reset pulse width ...

Page 74

... NXP Semiconductors START SCL SDA RESET rec(rst) Dn Fig 37. Reset timing SCL INT Fig 38. Interrupt timing PCA9665_3 Product data sheet as(int) Rev. 03 — 12 August 2008 PCA9665 2 Fm+ parallel bus to I C-bus controller ACK or read cycle rst w(rst) t rst off 30 % 002aab272 write to I2CCON ...

Page 75

... NXP Semiconductors (read) Fig 39. Bus timing (read cycle (write) Fig 40. Parallel bus timing (write cycle) PCA9665_3 Product data sheet t su( su(CE_N) t w(RDL d(DV) float not valid t su( su(CE_N) t w(WRL) WR Rev. 03 — 12 August 2008 PCA9665 Fm+ parallel bus h(CE_N) t w(RDH) t d(QZ) ...

Page 76

... NXP Semiconductors Fig 41. Data timing PCA9665_3 Product data sheet V I RD, CE input V M GND t d(QLZ output LOW-to-float float-to-LOW d(QHZ output HIGH-to-float float-to-HIGH GND outputs enabled and V are typical output voltage drops that occur with the output load Rev. 03 — 12 August 2008 ...

Page 77

... NXP Semiconductors 2 Table 51. I C-bus frequency and timing specifications All the timing limits are valid within the operating supply voltage and ambient temperature range; V 3 +85 C; and refer to V amb Symbol Parameter f SCL clock frequency SCL t bus free time between a ...

Page 78

... NXP Semiconductors SDA t LOW t f SCL t HD;STA S Fig 42. Definition of timing on the I START protocol condition ( SU;STA LOW SCL t BUF SDA t HD;STA Rise and fall times refer Fig 43. I C-bus timing diagram PCA9665_3 Product data sheet t SU;DAT SU;STA HIGH Sr t HD;DAT 2 C-bus ...

Page 79

... NXP Semiconductors 14. Test information Fig 44. Test circuitry for switching times Table 52. Test t d(DV) t d(QZ) Fig 45. Test circuitry for open-drain switching times Table 53. Test t d(DV) t d(QZ) t as(int) t das(int) PCA9665_3 Product data sheet V I PULSE GENERATOR R T Test data are given in Table 52. ...

Page 80

... NXP Semiconductors 15. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

Page 81

... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 82

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 83

... NXP Semiconductors HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 0.85 mm terminal 1 index area terminal 1 20 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 84

... NXP Semiconductors 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...

Page 85

... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...

Page 86

... NXP Semiconductors Fig 50. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Soldering of through-hole mount packages 18.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...

Page 87

... NXP Semiconductors 18.4 Package related soldering information Table 56. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. ...

Page 88

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 89

... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Internal oscillator . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 Registers 7.3.1 Direct registers . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.1.1 The Status register, I2CSTA ( ...

Page 90

... NXP Semiconductors 11 Limiting values Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 72 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 79 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 80 16 Handling information Soldering of SMD packages . . . . . . . . . . . . . . 84 17.1 Introduction to soldering . . . . . . . . . . . . . . . . . 84 17.2 Wave and reflow soldering . . . . . . . . . . . . . . . 84 17.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 84 17.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 85 18 Soldering of through-hole mount packages . 86 18.1 Introduction to soldering through-hole mount packages ...

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