MFRC52201HN1,157 NXP Semiconductors, MFRC52201HN1,157 Datasheet
MFRC52201HN1,157
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MFRC52201HN1
MFRC52201HN1
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MFRC52201HN1,157 Summary of contents
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MFRC522 Contactless Reader IC Rev. 3.2 — 22 May 2007 112132 1. Introduction This document describes the functionality of the contactless reader/writer MFRC522. It includes the functional and electrical specifications. 2. General description The MFRC522 is a highly integrated reader/writer ...
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... NXP Semiconductors SPI interface Mbit interface up to 400 kbit/s in Fast mode 3400 kbit/s in High-speed mode serial UART in different transfer speeds up to 1228.8 kbit/s, framing according to the RS232 interface with voltage levels according pad voltage supply Comfortable 64 byte send and receive FIFO-buffer ...
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... NXP Semiconductors 4. Quick reference data Table 1. Quick reference data Symbol Parameter AV Supply Voltage Pad power supply DD SV MFIN/MFOUT Pad Power DD Supply I Hard Power-down Current HPD I Soft Power-down Current SPD I Digital Supply Current DVDD I Analog Supply Current AVDD I Analog Supply Current, AVDD,RCVOFF ...
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... NXP Semiconductors 5. Ordering information Table 2: Ordering information Type number Package Name MFRC52201HN1/TRAYB HVQFN32 (delivered in 1 Tray) MFRC52201HN1/TRAYBM HVQFN32 (delivered in 5 Tray) 112132 Product data sheet Description see Package Outline in Figure 33 “Package outline package version (HVQFN32)” see Packing Information in Figure 34 “Packing Information 1 Tray” ...
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... NXP Semiconductors 6. Block diagram The Analog interface handles the modulation and demodulation of the analog signals. The contactless UART handles the protocol requirements for the communication schemes in co-operation with the host. The comfortable FIFO buffer allows a fast and convenient data transfer from the host to the contactless UART and vice versa. ...
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... NXP Semiconductors FIFO Control 64 Byte FIFO Control Register Bank MIFARE Classic Unit Random Number Generator Amplitude Rating Reference Voltage Analog Test MUX and DAC VMID AUX1,2 Fig 2. MFRC522 Block diagram 112132 Product data sheet SDA EA, I2C PVDD SPI, UART, I2C Interface Control ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1). 7.2 Pin description Table 3: Symbol PVDD DVDD DVSS PVSS NRSTPD MFIN MFOUT SVDD TVSS 112132 Product data sheet Pin description Pin Type Description [ I2C enable 2 PWR Pad power supply 3 PWR ...
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... NXP Semiconductors Table 3: Symbol TX1 TVDD TX2 TVSS AVDD VMID RX AVSS AUX1 AUX2 OSCIN OSCOUT IRQ SDA [1] Connection of heat sink pad on package buttom side is not necessary. Optional connection to DVSS is possible. [2] The pin functionality for the interfaces is explained in 112132 Product data sheet Pin description … ...
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... NXP Semiconductors 8. Functional description MFRC522 transmission module supports the Reader/Writer mode for ISO/IEC 14443A/MIFARE Battery Fig 4. MFRC522 Reader/Writer mode. The following diagram communication diagram.” ISO14443A Reader RC522 Fig 5. ISO/IEC 14443A/MIFARE The communication overview in ISO/IEC 14443A/MIFARE Table 4: Communication direction Reader → Card ...
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... NXP Semiconductors Table 4: Communication direction Card → Reader (MFRC522 receives data from a card) The contactless UART of MFRC522 and a dedicated external host are required to handle the complete MIFARE “Data Coding and framing according to ISO/IEC 14443A.” framing according to ISO/IEC 14443A / MIFARE®. ...
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... NXP Semiconductors 9. MFRC522 Register SET 9.1 MFRC522 Registers Overview Table 5: Addr (hex) Page 0: Command and Status Page 1: Command Page 2: CFG 0 112132 Product data sheet MFRC522 Registers Overview Register Name Function Reserved Reserved for future use CommandReg Starts and stops command execution ...
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... NXP Semiconductors Table 5: Addr (hex Page 3: TestRegister C-F 112132 Product data sheet MFRC522 Registers Overview …continued Register Name Function CRCResultReg Shows the actual MSB and LSB values of the CRC calculation Reserved Reserved for future use ModWidthReg Controls the setting of the ModWidth ...
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... NXP Semiconductors 9.1.1 Register Bit Behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In access conditions are described. Table 6: Abbreviation Behavior r RFU RFT 9.2 Register Description 9.2.1 Page 0: Command and Status 9 ...
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... NXP Semiconductors Table 9: Bit Symbol Access Rights Table 10: Bit 9.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 11: Bit Symbol Access Rights Table 12: Bit Symbol 7 IRqInv 6 TxIEn 5 RxIEn 4 IdleIEn 3 HiAlertIEn 112132 Product data sheet CommandReg register (address 01h); reset value: 20h ...
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... NXP Semiconductors Table 12: Bit Symbol 2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq ErrIEn 0 TimerIEn 112132 Product data sheet Description of CommIEnReg bits Description propagated to pin IRQ. Allows the error interrupt request (indicated by bit ErrIRq propagated to pin IRQ. Allows the timer interrupt request (indicated by bit TimerIRq propagated to pin IRQ. Rev. 3.2 — ...
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... NXP Semiconductors 9.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 13: Bit Symbol IRQPushPull Access Rights Table 14: Bit 9.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 15: Bit Symbol Access Rights Table 16: All bits in the register CommIRqReg shall be cleared by software. ...
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... NXP Semiconductors Table 16: All bits in the register CommIRqReg shall be cleared by software. Bit Symbol 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to 1 ErrIRq 0 TimerIRq 9.2.1.6 DivIRqReg Contains Interrupt Request bits Table 17: Bit Symbol Access Rights Table 18: All bits in the register DivIRqReg shall be cleared by software. ...
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... NXP Semiconductors 9.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 19: Bit Symbol Access Rights Table 20: Bit [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. 112132 Product data sheet ErrorReg register (address 06h); reset value: 00h ...
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... NXP Semiconductors 9.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO buffer. Table 21: Bit Symbol Access Rights Table 22: Bit 112132 Product data sheet Status1Reg register (address 07h); reset value: 21h CRCOk CRCReady RFU r r Description of Status1Reg bits Symbol Description - Reserved for future use. ...
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... NXP Semiconductors 9.2.1.9 Status2Reg Contains status bits of the receiver, transmitter and data mode detector. Table 23: Bit Symbol Access Rights Table 24: Bit Symbol 7 TempSensClear MFCrypto1On Modem State 112132 Product data sheet Status2Reg register (address 08h); reset value: 00h TempSens I CForceHS Clear r/w ...
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... NXP Semiconductors 9.2.1.10 FIFODataReg In- and output of 64 byte FIFO buffer. Table 25: Bit Symbol Access Rights Table 26: Bit 9.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 27: Bit Symbol FlushBuffer Access Rights Table 28: Bit 9.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. ...
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... NXP Semiconductors Table 30: Bit 9.2.1.13 ControlReg Miscellaneous control bits. Table 31: Bit Symbol TStopNow TStartNow Access Rights Table 32: Bit Symbol 7 TStopNow 6 TStartNow RxLastBits 112132 Product data sheet Description of WaterLevelReg bits Symbol Description - Reserved for future use. WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or ...
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... NXP Semiconductors 9.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 33: Bit Symbol Access Rights Table 34: Bit 9.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 35: Bit Symbol Access Rights Table 36: Bit Symbol 7 ValuesAfterColl CollPosNotValid 112132 Product data sheet BitFramingReg register (address 0Dh); reset value: 00h ...
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... NXP Semiconductors Table 36: Bit Symbol CollPos 9.2.1.16 Reserved Functionality is reserved for further use. Table 37: Bit Symbol Access Rights Table 38: Bit Symbol 9.2.2 Page 1: Communication 9.2.2.1 Reserved Functionality is reserved for further use. Table 39: Bit Symbol Access Rights Table 40: Bit Symbol 112132 Product data sheet ...
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... NXP Semiconductors 9.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 41: Bit Symbol MSBFirst Access Rights Table 42: Bit 9.2.2.3 TxModeReg Defines the data rate during transmission. Table 43: Bit Symbol TxCRCEn Access Rights 112132 Product data sheet ModeReg register (address 11h); reset value: 3Fh ...
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... NXP Semiconductors Table 44: Bit Symbol 7 TxCRCEn TxSpeed 3 InvMod 9.2.2.4 RxModeReg Defines the data rate during reception. Table 45: Bit Symbol RxCRCEn Access Rights Table 46: Bit 112132 Product data sheet Description of TxModeReg bits Description Set to logic 1, this bit enables the CRC generation during data transmission ...
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... NXP Semiconductors Table 46: Bit 9.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 47: Bit Symbol Access Rights Table 48: Bit 112132 Product data sheet Description of RxModeReg bits …continued Symbol Description RxNoErr If set to logic 1, a not valid received data stream (less than 4 bits received) will be ignored ...
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... NXP Semiconductors 9.2.2.6 TxASKReg Controls the settings of the transmit modulation. Table 49: Bit Symbol Access Rights Table 50: Bit 9.2.2.7 TxSelReg Selects the internal sources for the analog part. Table 51: Bit Symbol Access Rights Table 52: Bit Symbol DriverSel 112132 Product data sheet TxAutoReg register (address 15h); reset value: 00h ...
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... NXP Semiconductors Table 52: Bit Symbol MFOutSel 9.2.2.8 RxSelReg Selects internal receiver settings. Table 53: Bit Symbol Access Rights Table 54: Bit 112132 Product data sheet Description of TxSelReg bits Description Selects the input for the MFOUT Pin. Value Description 0000 Tristate 0001 Low 0010 ...
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... NXP Semiconductors 9.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 55: Bit Symbol Access Rights Table 56: Bit 9.2.2.10 DemodReg Defines demodulator settings. Table 57: Bit Symbol Access Rights Table 58: Bit Symbol AddIQ 5 FixIQ TauRcv TauSync 112132 Product data sheet RxThresholdReg register (address 18h); reset value: 84h ...
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... NXP Semiconductors 9.2.2.11 Reserved Functionality is reserved for further use. Table 59: Bit Symbol Access Rights Table 60: Bit Symbol 9.2.2.12 Reserved Functionality is reserved for further use. Table 61: Bit Symbol Access Rights Table 62: Bit Symbol 9.2.2.13 MfTxReg Controls some MIFARE Table 63: Bit Symbol Access ...
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... NXP Semiconductors 9.2.2.14 MfRxReg Table 65: Bit Symbol Access Rights Table 66: Bit 9.2.2.15 Reserved Functionality is reserved for further use. Table 67: Bit Symbol Access Rights Table 68: Bit 9.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 69: Bit Symbol Access Rights Table 70: ...
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... NXP Semiconductors 9.2.3 Page 2: Configuration 9.2.3.1 Reserved Functionality is reserved for further use. Table 71: Bit Symbol Access Rights Table 72: Bit 9.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Remark: The CRC is split into two 8-bit register. Table 73: ...
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... NXP Semiconductors 9.2.3.3 Reserved Functionality is reserved for further use. Table 77: Bit Symbol Access Rights Table 78: Bit 9.2.3.4 ModWidthReg Controls the setting of modulation width. Table 79: Bit Symbol Access Rights Table 80: Bit 9.2.3.5 Reserved Functionality is reserved for further use. Table 81: Bit Symbol Access ...
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... NXP Semiconductors 9.2.3.6 RFCfgReg Configures the receiver gain. Table 83: Bit Symbol Access Rights Table 84: Bit 9.2.3.7 GsNReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 85: Bit Symbol Access Rights Table 86: ...
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... NXP Semiconductors 9.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 87: Bit Symbol Access Rights Table 88: Bit 9.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 89: Bit Symbol Access Rights Table 90: Bit 112132 Product data sheet CWGsPReg register (address 28h); reset value: 20h ...
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... NXP Semiconductors 9.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Remark: The Prescaler value is split over two registers. Table 91: Bit Symbol Access Rights Table 92: Bit Symbol 7 TAuto TGated 4 TAutoRestart TPrescaler_Hi Defines higher 4 bits for TPrescaler. Table 93: Bit Symbol Access ...
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... NXP Semiconductors 9.2.3.11 TReloadReg Describes the 16 bit long timer reload value. Remark: The Reload value is split into two 8-bit registers. 00 Table 95: Bit Symbol Access Rights Table 96: Bit Table 97: Bit Symbol Access Rights Table 98: Bit 112132 Product data sheet TReloadReg (Higher bits) register (address 2Ch); reset value: 00h ...
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... NXP Semiconductors 9.2.3.12 TCounterValReg Contains the current value of the timer. Remark: The Counter value is split into two 8-bit register. Table 99: Bit Symbol Access Rights Table 100: Description of higher TCounterValReg bits Bit Table 101: TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh ...
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... NXP Semiconductors 9.2.4.2 TestSel1Reg General test signal configuration. Table 105: TestSel1Reg register (address 31h); reset value: 00h Bit Symbol Access Rights Table 106: Description of TestSel1Reg bits Bit 9.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 107: TestSel2Reg register (address 32h); reset value: 00h ...
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... NXP Semiconductors 9.2.4.4 TestPinEnReg Enables the pin output driver on the test bus. Table 109: TestPinEnReg register (address 33h); reset value: 80h Bit Symbol RS232LineEn Access Rights Table 110: Description of TestPinEnReg bits Bit 9.2.4.5 TestPinValueReg Defines the values for the test port when it is used as I/O. ...
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... NXP Semiconductors 9.2.4.6 TestBusReg Shows the status of the internal testbus. Table 113: TestBusReg register (address 35h); reset value: XXh Bit Symbol Access Rights Table 114: Description of TestBusReg bits Bit 9.2.4.7 AutoTestReg Controls the digital selftest. Table 115: AutoTestReg register (address 36h); reset value: 40h ...
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... NXP Semiconductors 9.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 119: AnalogTestReg register (address 38h); reset value: 00h Bit Symbol Access Rights Table 120: Description of AnalogTestReg bits Bit Symbol AnalogSelAux1 AnalogSelAux2 [1] Remark: Current output. The use of 1 kΩ pull-down resistor on AUX is recommended ...
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... NXP Semiconductors 9.2.4.10 TestDAC1Reg Defines the test values for TestDAC1. Table 121: TestDAC1Reg register (address 39h); reset value: XXh Bit Symbol Access Rights Table 122: Description of TestDAC1Reg bits Bit 9.2.4.11 TestDAC2Reg Defines the test value for TestDAC2. Table 123: TestDAC2Reg register (address 3Ah); reset value: XXh ...
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... NXP Semiconductors 9.2.4.13 Reserved Functionality reserved for production test. Table 127: Reserved register (address 3Ch); reset value: FFh Bit Symbol Access Rights Table 128: Description of Reserved register bits Bit Table 129: Reserved register (address 3Dh); reset value: 00h Bit Symbol Access ...
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... NXP Semiconductors 10. DIGITAL Interfaces 10.1 Automatic μ-Controller Interface Type Detection The MFRC522 supports direct interfacing of various hosts as the SPI, I UART interface type. The MFRC522 resets its interface and checks the current host interface type automatically having performed a Power-On or Hard Reset. The MFRC522 identifies the host interface by the means of the logic levels on the control pins after the Reset Phase ...
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... NXP Semiconductors 10.2.1 General An interface compatible to an SPI interface enables a high-speed serial communication between the MFRC522 and a μ-Controller for the communication. The implemented SPI compatible interface is according to a standard SPI interface. For timing specification refer to Fig 7. Connection to host with SPI The MFRC522 acts as a slave during the SPI communication ...
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... NXP Semiconductors 10.2.3 Write data To write data to the MFRC522 using the SPI interface the following byte order has to be used possible to write out up to n-data bytes by only sending one’s address byte. The first send byte defines both, the mode itself and the address byte. ...
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... NXP Semiconductors 10.3.2 Selection of the transfer speeds The internal UART interface is compatible to an RS232 serial interface. Table 140 “Selectable transfer speeds” and relevant register settings. The resulting transfer speed error is less than 1.5% for all described transfer speeds. The default transfer speed is 9.6 kbit/s. ...
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... NXP Semiconductors 10.3.3 Framing Table 141: UART Framing Start bit Data bits Stop bit Remark: For data and address bytes the LSB bit has to be sent first. Read data: To read out data using the UART interface the flow described below has to be used. The first send byte defines both the mode itself and the address ...
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... NXP Semiconductors Write data: To write data to the MFRC522 using the UART interface the following structure has to be used. The first send byte defines both, the mode itself and the address. Table 143: Byte Order to Write Data RX TX Fig 10. Schematic Diagram to Write Data. ...
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... NXP Semiconductors 2 10 Bus Interface An Inter IC (I interface to the host. The implemented I Semiconductors I interface can only act in Slave mode. Therefore no clock generation and access arbitration is implemented in the MFRC522. 2 Fig 11. I 10.4.1 General The implemented interface is conform to the I January 2000. The MFRC522 can act as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode ...
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... NXP Semiconductors 10.4.2 Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or LOW state of the data line shall only change when the clock signal on SCL is LOW. Fig 12. Bit transfer on the I 10.4.3 START and STOP conditions To handle the data transfer on the I are defined ...
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... NXP Semiconductors 10.4.4 Byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure 16 “First byte following the START transmitted bytes during one data transfer is unrestricted but shall fulfil the read/ write cycle format. ...
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... NXP Semiconductors Fig 15. Data transfer on the I 10.4.6 7-BIT ADDRESSING During the I to determine which slave will be selected by the master exception several address numbers are reserved. During device configuration, the designer has to ensure, that no collision with these reserved addresses is possible. Check the corresponding I ...
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... NXP Semiconductors Fig 16. First byte following the START procedure. 10.4.7 Register Write Access To write data from the host controller via I following frame format shall be used. The first byte of a frame indicates the device address according to the I second byte indicates the register address followed n-data bytes. In one frame all n-data bytes are written to the same register address ...
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... NXP Semiconductors 10.4.8 Register Read Access To read out data from a specific register address of the MFRC522 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame. The first byte of a frame indicates the device address according to the I second byte indicates the register address ...
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... NXP Semiconductors 10.4.9 HS mode In High-speed mode (HS mode) the device can transfer information at data rates 3.4 Mbit/s, it remains fully downward compatible with Fast- or Standard mode (F/S mode) for bi-directional communication in a mixed-speed bus system. 10.4.10 High Speed Transfer To achieve a data rates 3.4 Mbit/s the following improvements have been made to the regular I • ...
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... NXP Semiconductors 2 Fig 19 mode protocol frame 112132 Product data sheet Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC © NXP B.V. 2007. All rights reserved 109 ...
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... NXP Semiconductors 10.4.12 Switching from F mode and Vice Versa After reset and initialization, the MFRC522 is in Fast mode (which is in effect F/S mode as Fast mode is downward compatible to Standard mode). The connected MFRC522 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting ...
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... NXP Semiconductors 11. Analog Interface and Contactless UART 11.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. An external circuit can to be connected to the communication interface pins MFIN/MFOUT to modulate and demodulate the data ...
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... NXP Semiconductors Table 146: Settings for TX2 TX1RFEn Force TX2CW 100ASK The following abbreviations are used: • RF: 13.56 MHz clock derived from 27.12 MHz quartz divided by 2 • RF_n: inverted 13.56 MHz clock • gspmos: Conductance, configuration of the PMOS array • ...
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... NXP Semiconductors 11.3 Serial Data Switch Two main blocks are implemented in the MFRC522. A digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification circuitry. For example, the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins MFIN and MFOUT ...
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... NXP Semiconductors Remark: The MFRC522 has an extra supply pin (SVDD and PVSS as Ground line) for the M iller C oder Tx Bit Stream TestBus Serial data stream Tx Digital Part M FRC522 Serial data stream anchester R x Bit Stream D ecoder Fig 21. Overview MFIN/MFOUT Signal Routing 11.5 CRC co-processor The following parameters of the CRC co-processor can be configured ...
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... NXP Semiconductors 12. FIFO Buffer 12.1 Overview An 64 × 8-bit FIFO buffer is implemented in the MFRC522. It buffers the input and output data stream between the host and the internal state machine of the MFRC522. Thus possible to handle data streams with lengths bytes without taking timing constraints into account ...
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... NXP Semiconductors The bit HiAlert is set to logic 1 if maximum WaterLevel bytes (as set in register WaterLevelReg) or less can be stored in the FIFO-buffer generated according to the following equation: The bit LoAlert is set to logic 1 if WaterLevel bytes (as set in register WaterLevelReg) or less are actually stored in the FIFO-buffer generated according to the following ...
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... NXP Semiconductors 13. Timer Unit A timer unit is implemented in the MFRC522. The external host may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • ...
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... NXP Semiconductors 14. Interrupt Request System The MFRC522 indicates certain events by setting bit IRq in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. ...
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... NXP Semiconductors 15. Oscillator Circuitry The clock applied to the MFRC522 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry ...
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... NXP Semiconductors 16. Power Reduction modes 16.1 Hard Power-down A Hard Power-down is enabled with LOW level on pin NRSTPD. This turns off all internal current sinks as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin NRSTPD itself). The output pins are frozen at a certain value ...
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... NXP Semiconductors 17. Reset and Oscillator Startup Time 17.1 Reset Timing Requirements The reset signal is filtered by a hysteresis circuit and a spike filter (rejects signals shorter than 10 ns) before it enters the digital circuit. In order to perform a reset, the signal has to be low for at least 100 ns. ...
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... NXP Semiconductors 18. MFRC522 Command Set 18.1 General Description The behavior is determined by a state machine capable to perform a certain set of commands. By writing the according command-code to register CommandReg the command is executed. Arguments and/or data necessary to process a command are exchanged via the FIFO buffer. 18.2 General Behavior • ...
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... NXP Semiconductors 18.3.1 MFRC522 Command Description 18.3.1.1 Idle Command The MFRC522 is in Idle mode. This command is also used to terminate the actual command. 18.3.1.2 Mem Command Transfers 25 byte from the FIFO to the internal buffer. To read out the 25 byte from the internal buffer, the command Mem with an empty FIFO buffer has to be started ...
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... NXP Semiconductors 18.3.1.7 Receive Command The MFRC522activates the receiver path and waits for any data stream to be received. The correct settings have to be chosen before starting this command. This command terminates automatically when the received data stream ends. This is indicated either by the end of frame pattern or by the length byte depending on the selected framing and speed ...
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... NXP Semiconductors This command terminates automatically when the MIFARE bit MFCrypto1On in the Status2Reg register is set to This command does not terminate automatically when the card does not answer, therefore the timer should be initialized to automatic mode. In this case, beside the bit IdleIrq, the bit TimerIrq can be used as termination criteria. During authentication processing the bit RxIrq and bit TxIrq are blocked ...
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... NXP Semiconductors 19. Testsignals 19.1 Selftest The MFRC522 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. ...
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... NXP Semiconductors Table 151: Description of Testsignals Pins Table 152: TestSel2Reg register (address 0Dh) Pins Testsignal Table 153: Description of Testsignals Pins 19.3 Testsignals at pin AUX With the MFRC522, the user may select internal signals to measure them at pin AUX. These measurements can be helpful during the design-in phase to optimise the design or for test purpose ...
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... NXP Semiconductors Table 154: Testsignals description SelAux 1100 1101 1110 1111 112132 Product data sheet Description for Aux1 / Aux2 TxActive RxActive Subcarrier detected TstBusBit Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC © NXP B.V. 2007. All rights reserved 109 ...
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... NXP Semiconductors 19.3.1 Example: Output TestDAC 1 on AUX1 and TestDAC 2 on AUX2 Register AnalogTestReg is set to 11h. The output of AUX1 corresponds to the TestDAC 1 and the output of AUX2 to the TestDAC 2. The value of TestDAC 1 and TestDAC 2 is controlled by register TestDAC1Reg and TestDAC2Reg. Figure 24 has been programmed with a rectangular signal with values of 00h and 3Fh. ...
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... NXP Semiconductors Fig 25. Output Testsignal Corr1 on AUX1 and MinLevel on AUX2. 19.3.3 Example: Output ADC channel I on AUX 1 and ADC channel Q on AUX 2 Figure 26 56h. Fig 26. Output ADC channel I on AUX 1 and ADC channel Q on AUX 2. 112132 Product data sheet shows the ADC_I and ADC_Q channel behaviour. The AnalogTestReg is set to Rev. 3.2 — ...
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... NXP Semiconductors 19.3.4 Example: Output RxActive on AUX 1 and TxActive on AUX 2 The following communication. The AnalogTestReg was set to CDh. Remark: At 106 kbit/s, RxActive is HIGH during databits, parity and CRC reception. Fig 27. Output RxActive on AUX 1 and TxActive on AUX 2. 112132 Product data sheet Figure 27 shows the RXActive and TXActive signal in accordance to the RF Startbits are not included ...
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... NXP Semiconductors 19.3.5 Example: Output Rx Data Stream on AUX 1 and AUX 2 The following to enable certain digital test data on D1-D6 (see TestSel1Reg is set to 06h (D6 = sdata) and AnalogTestReg is set to FFh to output the received data stream to pin AUX1 and AUX2. Fig 28. Output Rx data stream on AUX 1 and AUX 2. ...
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... NXP Semiconductors 20. Limiting values Table 155. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter AV Supply voltage Input voltage in V Input voltage in,MFIN P Total power dissipation per package tot (V and DV in short cut mode) BUS DD T Junction temperature range J ESD Susceptibility (Human Body model) 1500 Ω ...
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... NXP Semiconductors 23. Characteristics 23.1 Input Pin Characteristics 23.1.1 Input Pin characteristics for pins EA, I2C and NRESET Table 158: Input Pin characteristics for pins EA, I2C and NRESET Symbol I Leak 23.1.2 Input Pin characteristics for pin MFIN Table 159: Input Pin characteristics for MFIN ...
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... NXP Semiconductors 23.1.5 Output Pin characteristics for Pin MFOUT Table 162: Output Pin characteristics for Pin MFOUT Symbol Parameter V Output voltage HIGH Output voltage LOW Output current drive OL LOW I Output current drive OH HIGH 23.1.6 Output Pin characteristics for Pin IRQ Table 163: Output Pin characteristics for Pin IRQ ...
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... NXP Semiconductors Table 165: Input Pin characteristics for OSCIN Symbol OSCIN 23.1.9 Output Pin characteristics for Pins AUX1 and AUX2 Table 166: Output Pin characteristics for Pins AUX1 and AUX2 Symbol Parameter V Output voltage HIGH Output voltage LOW OL I Output current drive ...
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... NXP Semiconductors 23.2 Current Consumption Table 168: Current Consumption Symbol I HPD I SPD I DVDD I AVDD I AVDD,RCVOFF I PVDD I TVDD I SVDD [1] I depends on TV TVDD [2] I depends on the overall load at the digital pins. PVDD [3] During operation with a typical circuitry the overall current is below 100 mA. ...
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... NXP Semiconductors 23.3 RX Input Voltage Range Table 169: RX Input Voltage Range Symbol V RX,MinIV,Man V RX,MaxIV,Man Figure 29 Fig 29. RX Input Voltage Range 23.4 RX Input Sensitivity Table 170: RX Input Sensitivity Symbol V RXMod,Man Figure 29 23.5 Clock Frequency Table 171: Clock Frequency Symbol f OSCIN d FEC t jitter ...
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... NXP Semiconductors 23.6 XTAL Oscillator Table 172: XTAL Oscillator Symbol V OH,OSCOUT V OL,OSCOUT C IN,OSCOUT C IN,OSCIN 23.7 Typical 27.12 MHz Crystal Requirements Table 173: XTAL Oscillator Symbol f XTAL ESR XTAL 112132 Product data sheet Parameter Conditions Output Voltage High XTAL2 Output Voltage Low XTAL2 ...
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... NXP Semiconductors 23.8 Timing for the SPI compatible interface Table 174: Timing Specification for SPI Symbol t SCKL t SCKH t SHDX t DXSH t SLDX t SLNH SCK MOSI MISO NSS Remark: The signal NSS has to be low to be able to send several bytes in one datastream. To send more than one datastream NSS has to be set to HIGH level in between the data streams ...
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... NXP Semiconductors 2 23 Timing Table 175. Overview I Symbol Parameter f SCL clock frequency SCL t Hold time (repeated) START condition. HD;STA After this period, the first clock pulse is generated t Set-up time for a repeated START SU;STA condition t Set-up time for STOP condition SU;STO t LOW period of the SCL clock ...
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... NXP Semiconductors 24. Application information The figure below shows a typical circuit diagram, using a complementary antenna connection to the MFRC522. The antenna tuning and RF part matching is described in the application note Ref. 2. µ- Host Interface Processor IR Q IRQ Fig 32. Typical Application Circuit Diagram 112132 Product data sheet ...
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... NXP Semiconductors 25. Package outline Fig 33. Package outline package version (HVQFN32) Detailed package information can be found on NXP Internet http://www.nxp.com/package/SOT617-1.html 112132 Product data sheet Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC © NXP B.V. 2007. All rights reserved 109 ...
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... NXP Semiconductors 26. Handling information Moisture Sensitivity Level (MSL) Evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which means 260 °C convection reflow temperature. Dry pack is not required. Unlimited out of pack Floor Life at maximum ambient 30 °C/85%RH. ...
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... NXP Semiconductors 27. Packing information Fig 34. Packing Information 1 Tray 112132 Product data sheet Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC © NXP B.V. 2007. All rights reserved 109 ...
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... NXP Semiconductors Fig 35. Packing Information 5Tray 112132 Product data sheet Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC © NXP B.V. 2007. All rights reserved 109 ...
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... NXP Semiconductors 28. Abbreviations Table 176: Abbreviations Acronym ASK PCD PICC PCD Æ PICC PICCÆ PCD Modulation Index The modulation index is defined as the voltage ratio (Vmax - Vmin)/ Loadmodulation Index 29. References [ MFRC52x Reader IC Family Directly Matched Antenna Design — Application note for Mifare MFRC52x Reader IC Antenna Design [ Mifare(14443A) 13,56 MHz RFID Proximity Antennas — ...
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... NXP Semiconductors 30. Revision history Table 177: Revision history Document ID Release date 112132 Mai 2007 • correction Interface PIN order in Types” • correction Table 137 • removed D0 from • removed 212, 424, 848 kbaud from • correction typical application circuit diagram • ...
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... NXP Semiconductors Table 177: Revision history …continued Document ID Release date • temporary remove type ordering information • changes in register description • adaptation figure 22 112103 October 2004 • changes in register description 112132 Product data sheet Data sheet status Change notice Rev. 3.2 — 22 May 2007 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ...
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... NXP Semiconductors 32. Contact information For additional information, please visit: For sales office addresses, send an email to: 112132 Product data sheet http://www.nxp.com sales.addresses@www.nxp.com Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC continued >> © NXP B.V. 2007. All rights reserved. 101 of 109 ...
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... NXP Semiconductors 112132 Product data sheet Notes Rev. 3.2 — 22 May 2007 MFRC522 Contactless Reader IC continued >> © NXP B.V. 2007. All rights reserved. 102 of 109 ...
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... NXP Semiconductors 33. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . 3 Table 2: Ordering information . . . . . . . . . . . . . . . . . 4 Table 3: Pin description . . . . . . . . . . . . . . . . . . . . . . 7 Table 4: Communication overview for ISO/IEC 14443A/MIFARE® reader/writer . . . . . . . . 9 Table 5: MFRC522 Registers Overview . . . . . . . . 11 Table 6: Behavior of Register Bits and its Designation 13 Table 7: Reserved register (address 00h); reset value: 00h Table 8: Description of Reserved register bits . . . . 13 Table 9: CommandReg register (address 01h) ...
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... NXP Semiconductors Table 64: Description of MifNFCReg bits . . . . . . . . . 31 Table 65: MfRxReg register (address 1Dh); reset value: 00h Table 66: Description of ManualRCVReg bits . . . . . 32 Table 67: Reserved register (address 1Eh); reset value: 00h Table 68: Description of Reserved register bits . . . . 32 Table 69: SerialSpeedReg register (address 1Fh); reset value: EBh . . . . . . . . . . . . . . . . . . . . 32 Table 70: Description of SerialSpeedReg bits . . . . . 32 Table 71: Reserved register (address 20h) ...
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... NXP Semiconductors Table 131: Reserved register (address 3Eh); reset value: 03h Table 132:Description of Reserved register bits . . . 45 Table 133:Reserved register (address 3Fh); reset value: 00h Table 134:Description of Reserved register bits . . . 45 Table 135:Connection Scheme for detecting the different Interface Types . . . . . . . . . . . . . . 46 Table 136:Byte Order for MOSI and MISO . . . . . . . 47 Table 137:Byte Order for MOSI and MISO . . . . . . . 48 Table 138.Address byte 0 register ...
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... NXP Semiconductors 34. Figures Fig 1. Simplified MFRC522 Block diagram . . . . . . . 5 Fig 2. MFRC522 Block diagram . . . . . . . . . . . . . . . 6 Fig 3. Pinning configuration HVQFN32 (SOT617-1). 7 Fig 4. MFRC522 Reader/Writer mode Fig 5. ISO/IEC 14443A/MIFARE® Reader/Writer mode communication diagram Fig 6. Data Coding and framing according to ISO/IEC 14443A Fig 7. Connection to host with SPI . . . . . . . . . . . . 47 Fig 8 ...
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... NXP Semiconductors 35. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . 1 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . 3 5 Ordering information . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description Functional description . . . . . . . . . . . . . . . . . 9 9 MFRC522 Register SET . . . . . . . . . . . . . . 11 9.1 MFRC522 Registers Overview . . . . . . . . . 11 9.1.1 Register Bit Behavior . . . . . . . . . . . . . . . . 13 9 ...
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... NXP Semiconductors 10.2.4 Address byte . . . . . . . . . . . . . . . . . . . . . . . 48 10.3 UART Interface . . . . . . . . . . . . . . . . . . . . . 48 10.3.1 Connection to a host . . . . . . . . . . . . . . . . . 48 10.3.2 Selection of the transfer speeds . . . . . . . . 49 10.3.3 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . 52 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.4.2 Data validity 10.4.3 START and STOP conditions . . . . . . . . . . 53 10.4.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 54 10.4.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . 54 10.4.6 7-BIT ADDRESSING ...
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... NXP Semiconductors 23.1.9 Output Pin characteristics for Pins AUX1 and AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 23.1.10Output Pin characteristics for Pins TX1 and TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 23.2 Current Consumption . . . . . . . . . . . . . . . . 87 23.3 RX Input Voltage Range . . . . . . . . . . . . . . 88 23.4 RX Input Sensitivity . . . . . . . . . . . . . . . . . . 88 23.5 Clock Frequency . . . . . . . . . . . . . . . . . . . . 88 23.6 XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . 89 23.7 Typical 27.12 MHz Crystal Requirements . 89 23 ...